公开(公告)号：US07574571B2

公开(公告)日：2009-08-11

申请号：US11289797

申请日：2005-11-30

申请人： Kenneth W. Batcher

发明人： Kenneth W. Batcher

IPC分类号： G06F12/16 ,  H04L9/00

CPC分类号： H04L9/065 ,  H04L2209/125

摘要： A system for the encryption and decryption of data employing dual ported RAM to accelerate data processing operations during the computation of the encryption and decryption algorithm. The system includes logic to track data changes in the dual ported memory for fast table initialization; a means to accelerate operations by performing read/write operations in different iterations of the algorithm to separate ports on the dual ported RAM in the same clock cycle; and a means to resolve data manipulation conflicts between out of order read/write operations so that the system correctly computes the desired algorithm.

摘要翻译： 一种用于加密和解密采用双端口RAM的数据的系统，用于在计算加密和解密算法期间加速数据处理操作。 该系统包括用于跟踪双端口存储器中的数据变化的逻辑，用于快速表初始化; 通过在该算法的不同迭代中执行读/写操作来加速操作的手段，以在同一时钟周期内分离双端口RAM上的端口; 以及解决数据处理在无序读/写操作之间冲突的手段，以便系统正确计算所需的算法。

公开(公告)号：US07010579B1

公开(公告)日：2006-03-07

申请号：US09669350

申请日：2000-09-26

申请人： Kenneth W. Batcher

发明人： Kenneth W. Batcher

IPC分类号： G06F15/16 ,  G06F9/26

CPC分类号： G06F9/30032 ,  G06F9/30043

摘要： A system of data transfer between a first processing device and a second processing device which speeds data transfer by eliminating intermediate storage steps. A plurality of memory storage devices are provided between the first and second processing devices for the purpose of synchronization and alignment. One of the memory storage devices is associated with the second processing device. In accordance with a first embodiment of the present invention, a new instruction is provided to implement a data transfer function for transferring data directly between a first memory storage device and a second memory storage device, without intermediate storage in a processor register. Thereafter, the data is transferred from the second memory storage device to the memory storage device associated with the second processing device. In accordance with a second embodiment of the present invention, data is efficiently transferred directly between a first memory storage device and the memory storage device associated with the second processing device, without intermediate storage in either a processor register or a second memory storage device.

摘要翻译： 一种在第一处理装置和第二处理装置之间的数据传送系统，其通过消除中间存储步骤来加速数据传送。 为了同步和对准的目的，在第一和第二处理装置之间提供多个存储器存储装置。 存储器存储设备之一与第二处理设备相关联。 根据本发明的第一实施例，提供了一种新的指令来实现用于在第一存储器存储设备和第二存储器设备之间直接传送数据的数据传输功能，而无需在处理器寄存器中进行中间存储。 此后，数据从第二存储器存储设备传送到与第二处理设备相关联的存储器存储设备。 根据本发明的第二实施例，数据在第一存储器存储设备和与第二处理设备相关联的存储器存储设备之间直接有效地传送，而无需在处理器寄存器或第二存储器存储设备中进行中间存储。

公开(公告)号：US06269043B1

公开(公告)日：2001-07-31

申请号：US09629715

申请日：2000-07-31

申请人： Kenneth W. Batcher

发明人： Kenneth W. Batcher

IPC分类号： G11C700

CPC分类号： G06F1/324 ,  G06F1/3203 ,  Y02D10/126

摘要： A power conservation system which provides for fast and efficient transitions between fast and slow processor clocking speeds. The slow processor clocking speed minimizes power consumption during periods of processor inactivity (idle states) or low priority execution. The fast processor clocking speeds are utilized during periods of processor activity (active states) or high priority execution. Used in conjunction with a context-sensitive processor, the power conservation system is able to monitor the state of the processor and modify the processor clocking speed accordingly.

摘要翻译： 一种省电系统，可在快速和慢速的处理器时钟速度之间实现快速有效的转换。 缓慢的处理器时钟速度使处理器不活动（空闲状态）或低优先级执行期间的功耗最小化。 快速处理器时钟速度在处理器活动（活动状态）或高优先级执行期间被使用。 与上下文相关的处理器结合使用，省电系统能够监控处理器的状态并相应地修改处理器时钟速度。

公开(公告)号：US20090180620A1

公开(公告)日：2009-07-16

申请号：US12409660

申请日：2009-03-24

申请人： Kenneth W. Batcher

发明人： Kenneth W. Batcher

IPC分类号： H04L9/06 ,  G06F12/14

CPC分类号： H04L9/065 ,  H04L2209/12 ,  H04L2209/80

摘要： A system for the encryption and decryption of data employing dual ported RAM for key storage to accelerate data processing operations. The on-chip key storage includes a dual-ported memory device which allows keys to be loaded into memory simultaneous with keys being read out of memory. Thus, an encryption or decryption algorithm can proceed while keys are being loaded into memory.

摘要翻译： 一种用于加密和解密采用双端口RAM进行密钥存储的数据加速数据处理操作的系统。 片上密钥存储器包括双端口存储器件，其允许将键加载到存储器中，同时将键读出存储器。 因此，当密钥被加载到存储器中时，可以进行加密或解密算法。

公开(公告)号：US07051181B2

公开(公告)日：2006-05-23

申请号：US11036289

申请日：2005-01-14

申请人： Kenneth W. Batcher

发明人： Kenneth W. Batcher

IPC分类号： G06F12/00

CPC分类号： G06F9/461 ,  G06F12/0842

摘要： Techniques for implementing caches for context switching applications are provided. A context identifier is stored in the cache to indicate the context to which data in the cache is associated. Additionally, the context can have different priorities so that storage space in the cache can be more efficiently allocated to the contexts based on their priorities.

摘要翻译： 提供了用于实现上下文切换应用的高速缓存的技术。 上下文标识符被存储在高速缓存中以指示高速缓存中哪个数据被关联的上下文。 另外，上下文可以具有不同的优先级，使得缓存中的存储空间可以基于它们的优先级更有效地分配给上下文。

公开(公告)号：US07006634B1

公开(公告)日：2006-02-28

申请号：US09675069

申请日：2000-09-28

申请人： Kenneth W. Batcher

发明人： Kenneth W. Batcher

IPC分类号： H04L9/00

CPC分类号： H04L9/065 ,  H04L2209/12 ,  H04L2209/80

摘要： A system for the encryption and decryption of data employing dual ported RAM for key storage to accelerate data processing operations. The on-chip key storage includes a dual-ported memory device which allows keys to be loaded into memory simultaneous with keys being read out of memory. Thus, an encryption or decryption algorithm can proceed while keys are being loaded into memory.

公开(公告)号：US5933347A

公开(公告)日：1999-08-03

申请号：US876155

申请日：1997-06-13

申请人： William B. Cook ,  Mark A. Flood ,  Kenneth W. Batcher

发明人： William B. Cook ,  Mark A. Flood ,  Kenneth W. Batcher

IPC分类号： G05B9/03 ,  G05B19/05 ,  G05B9/02

CPC分类号： G05B9/03 ,  G05B19/058 ,  G05B2219/14131 ,  G05B2219/15079 ,  G05B2219/21105

摘要： An industrial control system employs a primary and secondary controller each having a processor and an I/O data table. Updating of the secondary processor's I/O data table is accomplished synchronously with execution of the program in the primary processor at a particular point in the program. A tracking of changes in the I/O data table of the primary processor is used to transmit only changes in the I/O table to the secondary processor thereby avoiding undue interruption of the executing program while preserving synchronicity.

摘要翻译： 工业控制系统采用具有处理器和I / O数据表的主控制器和次控制器。 辅助处理器的I / O数据表的更新与程序中特定点的主处理器中程序的执行同步完成。 使用主处理器的I / O数据表中的变化的跟踪仅将I / O表中的变化传送到二级处理器，从而避免执行程序的不适当中断，同时保持同步。

公开(公告)号：US07472027B1

公开(公告)日：2008-12-30

申请号：US10854448

申请日：2004-05-26

申请人： Kenneth W. Batcher ,  Peter W. Ecclesine

发明人： Kenneth W. Batcher ,  Peter W. Ecclesine

IPC分类号： G01R21/00 ,  H04B17/00 ,  H04J13/00

CPC分类号： H04W16/14 ,  H04B1/715 ,  H04B17/345 ,  H04W24/00 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/40

摘要： A method and implementation disclosed for detecting interference. A state machine controller is provided for establishing an interference detection cycle including a power sample period and a periodic sampling interval. A receiver component, responsive to the state machine controller, performs an energy measurement at a predetermined wireless band during the power sample period. A threshold comparator determines whether the energy measurement exceeds a predetermined threshold. A processing implementation processes the energy measurement to determine whether it corresponds to interference on the predetermined wireless band, if the measurement exceeds the predetermined threshold. A deactivating implementation is used to instruct the state machine controller to await the next power sample period, if the energy measurement does not exceed the predetermined threshold.

摘要翻译： 公开的用于检测干扰的方法和实现。 提供状态机控制器，用于建立包括功率采样周期和周期性采样间隔的干扰检测周期。 响应于状态机控制器的接收器部件在功率采样周期期间在预定的无线频带执行能量测量。 阈值比较器确定能量测量是否超过预定阈值。 如果测量超过预定阈值，则处理实现处理能量测量以确定其是否对应于预定无线频带上的干扰。 如果能量测量不超过预定阈值，则使用去激活实现来指示状态机控制器等待下一个功率采样周期。

公开(公告)号：US06944688B1

公开(公告)日：2005-09-13

申请号：US09861149

申请日：2001-05-18

申请人： Kenneth W. Batcher

发明人： Kenneth W. Batcher

IPC分类号： G06F3/00 ,  G06F5/00 ,  H04L29/06

CPC分类号： H04L9/0618 ,  H04L49/901 ,  H04L63/0457 ,  H04L69/22 ,  H04L2209/12

摘要： A queuing system utilizing dual first-in, first-out (FIFO) memories is provided. The present queuing system is configured to use a first FIFO memory to receive and transfer a plurality of frames to a second FIFO memory wherein the frames include encrypted frame contents. The first FIFO memory is configured to transfer an interrupt to an associated processor in response to completion of the receipt of a valid frame. Next, the processor is configured to reinitialize the first FIFO memory for receipt of a subsequent frame.Additionally, the second FIFO memory is suitably adapted to concurrently store a plurality of frames transferred from the first FIFO memory. Finally, the present system is configured to transfer one of the stored frames out of the second FIFO memory in response to the completion of a data processing operation (e.g. initialization of a decryption algorithm).

摘要翻译： 提供了利用双先进先出（FIFO）存储器的排队系统。 当前排队系统被配置为使用第一FIFO存储器来接收并将多个帧传送到第二FIFO存储器，其中帧包括加密的帧内容。 响应于接收到有效帧的完成，第一FIFO存储器被配置为将中断传送到相关联的处理器。 接下来，处理器被配置为重新初始化第一FIFO存储器以接收后续帧。 另外，第二FIFO存储器适合于同时存储从第一FIFO存储器传送的多个帧。 最后，本系统被配置为响应于数据处理操作的完成（例如解密算法的初始化）将所存储的帧中的一个传送出第二FIFO存储器。

公开(公告)号：US06857046B1

公开(公告)日：2005-02-15

申请号：US10109318

申请日：2002-03-28

申请人： Kenneth W. Batcher

发明人： Kenneth W. Batcher

IPC分类号： G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/461 ,  G06F12/0842

摘要： Techniques for implementing caches for context switching applications are provided. A context identifier is stored in the cache to indicate the context to which data in the cache is associated. Additionally, the context can have different priorities so that storage space in the cache can be more efficiently allocated to the contexts based on their priorities.

摘要翻译： 提供了用于实现上下文切换应用的高速缓存的技术。 上下文标识符被存储在高速缓存中以指示高速缓存中哪个数据被关联的上下文。 另外，上下文可以具有不同的优先级，使得缓存中的存储空间可以基于它们的优先级更有效地分配给上下文。