SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    半导体器件及其形成方法

    公开(公告)号:US20080272430A1

    公开(公告)日:2008-11-06

    申请号:US12111120

    申请日:2008-04-28

    IPC分类号: H01L29/78

    CPC分类号: H01L29/4236 H01L29/66621

    摘要: A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench.

    摘要翻译: 半导体器件包括限定在衬底中的有源区,有源区具有在衬底的表面下方延伸的沟槽; 沿着沟槽的底表面和下侧壁设置的杂质区,其中杂质区的上部与衬底的表面和沟槽的上部间隔开; 栅极绝缘层,沿着沟槽的内表面设置; 以及设置在沟槽中的栅电极。

    Semiconductor device and methods thereof
    2.
    发明申请
    Semiconductor device and methods thereof 失效
    半导体器件及其方法

    公开(公告)号:US20070278599A1

    公开(公告)日:2007-12-06

    申请号:US11785304

    申请日:2007-04-17

    申请人: Ki-Jae Hur

    发明人: Ki-Jae Hur

    摘要: A semiconductor device and method of forming the same are provided. The example semiconductor device may include a gate pattern including a gate electrode and a capping layer pattern on a semiconductor substrate, a spacer covering first and second sidewalls of the gate pattern, an impurity injection region formed in the semiconductor substrate adjacent to the gate pattern and an etch stopping layer covering a surface of the semiconductor substrate adjacent to the spacer, the etch stopping layer substantially not covering the first and second sidewalls of the spacer and an upper surface of the capping layer pattern. An example method of forming a semiconductor device may include selectively forming an etch stopping layer in a semiconductor substrate by injecting ions into the semiconductor substrate, the semiconductor substrate having a composition which reacts with the injected ions to form the etch stopping layer, the injected ions also injected into structural elements mounted on the semiconductor substrate, the structural elements having a composition which does not react with the injected ions to form the etch stopping layer.

    摘要翻译: 提供一种半导体器件及其制造方法。 示例性半导体器件可以包括在半导体衬底上包括栅电极和覆盖层图案的栅极图案,覆盖栅极图案的第一和第二侧壁的间隔物,形成在与栅极图案相邻的半导体衬底中的杂质注入区域,以及 覆盖所述半导体衬底的与所述间隔物相邻的表面的蚀刻停止层,所述蚀刻停止层基本上不覆盖所述间隔物的第一和第二侧壁以及所述覆盖层图案的上表面。 形成半导体器件的示例性方法可以包括通过将离子注入到半导体衬底中来选择性地在半导体衬底中形成蚀刻停止层,该半导体衬底具有与注入的离子反应以形成蚀刻停止层的组成,注入的离子 也注入到安装在半导体衬底上的结构元件中,结构元件具有不与注入离子反应形成蚀刻停止层的组成。

    Asymmetric field effect transistor
    3.
    发明授权
    Asymmetric field effect transistor 失效
    非对称场效应晶体管

    公开(公告)号:US07145196B2

    公开(公告)日:2006-12-05

    申请号:US11003612

    申请日:2004-12-02

    IPC分类号: H01L27/108

    摘要: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

    摘要翻译: 场效应晶体管包括形成在半导体结构上的栅堆叠下的沟道区。 场效应晶体管还包括形成有掺杂沟道区的第一侧的第一掺杂物的漏极区,并且包括形成有掺杂沟道区的第二侧的第一掺杂剂的源极区。 漏极和源极区域被非对称地掺杂,使得沟道和漏极区域之间的第一电荷载流子谱具有比沟道和源极区域之间的第二电荷载流子谱更陡峭的斜率。

    Bottom electrode of capacitor of semiconductor device and method of forming the same
    4.
    发明申请
    Bottom electrode of capacitor of semiconductor device and method of forming the same 审中-公开
    半导体器件电容器底电极及其形成方法

    公开(公告)号:US20050263814A1

    公开(公告)日:2005-12-01

    申请号:US11175816

    申请日:2005-07-05

    摘要: To form a bottom electrode of a capacitor of a semiconductor device, a first insulation layer pattern having a first contact hole is formed on a substrate, and a contact plug for the bottom electrode is formed in the contact hole. A second insulation layer is formed on the first insulation layer pattern and the contact plug. The second insulation layer has a second etching rate higher than a first etching rate of the first insulation layer pattern. The second insulation layer is etched to form a second insulation layer pattern having a second a contact hole exposing the contact plug. A conductive film is formed on the sidewall and the bottom face of the second contact hole. According to the difference between the first etching rate and the second etching rate, the etching of the first insulation layer pattern near the contact plug is reduced.

    摘要翻译: 为了形成半导体器件的电容器的底部电极,在基板上形成具有第一接触孔的第一绝缘层图案,并且在接触孔中形成用于底部电极的接触插塞。 在第一绝缘层图案和接触插塞上形成第二绝缘层。 第二绝缘层具有比第一绝缘层图案的第一蚀刻速率高的第二蚀刻速率。 蚀刻第二绝缘层以形成第二绝缘层图案,其具有暴露接触插塞的第二接触孔。 导电膜形成在第二接触孔的侧壁和底面上。 根据第一蚀刻速率和第二蚀刻速度之间的差异,减小了接触插头附近的第一绝缘层图案的蚀刻。

    Semiconductor device including a selectively formed ETCH stopping layer and methods thereof
    5.
    发明授权
    Semiconductor device including a selectively formed ETCH stopping layer and methods thereof 失效
    包括选择性地形成的ETCH停止层的半导体器件及其方法

    公开(公告)号:US07786517B2

    公开(公告)日:2010-08-31

    申请号:US11785304

    申请日:2007-04-17

    申请人: Ki-Jae Hur

    发明人: Ki-Jae Hur

    IPC分类号: H01L29/78

    摘要: A semiconductor device and method of forming the same are provided. The example semiconductor device may include a gate pattern including a gate electrode and a capping layer pattern on a semiconductor substrate, a spacer covering first and second sidewalls of the gate pattern, an impurity injection region formed in the semiconductor substrate adjacent to the gate pattern and an etch stopping layer covering a surface of the semiconductor substrate adjacent to the spacer, the etch stopping layer substantially not covering the first and second sidewalls of the spacer and an upper surface of the capping layer pattern. An example method of forming a semiconductor device may include selectively forming an etch stopping layer in a semiconductor substrate by injecting ions into the semiconductor substrate, the semiconductor substrate having a composition which reacts with the injected ions to form the etch stopping layer, the injected ions also injected into structural elements mounted on the semiconductor substrate, the structural elements having a composition which does not react with the injected ions to form the etch stopping layer.

    摘要翻译: 提供一种半导体器件及其制造方法。 示例性半导体器件可以包括在半导体衬底上包括栅电极和覆盖层图案的栅极图案,覆盖栅极图案的第一和第二侧壁的间隔物,形成在与栅极图案相邻的半导体衬底中的杂质注入区域,以及 覆盖所述半导体衬底的与所述间隔物相邻的表面的蚀刻停止层,所述蚀刻停止层基本上不覆盖所述间隔物的第一和第二侧壁以及所述覆盖层图案的上表面。 形成半导体器件的示例性方法可以包括通过将离子注入到半导体衬底中来选择性地在半导体衬底中形成蚀刻停止层,该半导体衬底具有与注入的离子反应以形成蚀刻停止层的组成,注入的离子 也注入到安装在半导体衬底上的结构元件中,结构元件具有不与注入离子反应形成蚀刻停止层的组成。

    Method of forming semiconductor device capacitor bottom electrode having cylindrical shape
    6.
    发明授权
    Method of forming semiconductor device capacitor bottom electrode having cylindrical shape 失效
    形成具有圆柱形状的半导体器件电容器底部电极的方法

    公开(公告)号:US06930014B2

    公开(公告)日:2005-08-16

    申请号:US10670485

    申请日:2003-09-24

    摘要: To form a bottom electrode of a capacitor of a semiconductor device, a first insulation layer pattern having a first contact hole is formed on a substrate, and a contact plug for the bottom electrode is formed in the contact hole. A second insulation layer is formed on the first insulation layer pattern and the contact plug. The second insulation layer has a second etching rate higher than a first etching rate of the first insulation layer pattern. The second insulation layer is etched to form a second insulation layer pattern having a second a contact hole exposing the contact plug. A conductive film is formed on the sidewall and the bottom face of the second contact hole. According to the difference between the first etching rate and the second etching rate, the etching of the first insulation layer pattern near the contact plug is reduced.

    摘要翻译: 为了形成半导体器件的电容器的底部电极,在基板上形成具有第一接触孔的第一绝缘层图案,并且在接触孔中形成用于底部电极的接触插塞。 在第一绝缘层图案和接触插塞上形成第二绝缘层。 第二绝缘层具有比第一绝缘层图案的第一蚀刻速率高的第二蚀刻速率。 蚀刻第二绝缘层以形成第二绝缘层图案,其具有暴露接触插塞的第二接触孔。 导电膜形成在第二接触孔的侧壁和底面上。 根据第一蚀刻速率和第二蚀刻速度之间的差异,减小了接触插头附近的第一绝缘层图案的蚀刻。

    Methods of forming an asymmetric field effect transistor
    7.
    发明授权
    Methods of forming an asymmetric field effect transistor 失效
    形成不对称场效应晶体管的方法

    公开(公告)号:US07442613B2

    公开(公告)日:2008-10-28

    申请号:US11586359

    申请日:2006-10-25

    IPC分类号: H01L21/336

    摘要: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

    摘要翻译: 场效应晶体管包括形成在半导体结构上的栅堆叠下的沟道区。 场效应晶体管还包括形成有掺杂沟道区的第一侧的第一掺杂物的漏极区,并且包括形成有掺杂沟道区的第二侧的第一掺杂剂的源极区。 漏极和源极区域被非对称地掺杂,使得沟道和漏极区域之间的第一电荷载流子谱具有比沟道和源极区域之间的第二电荷载流子谱更陡峭的斜率。

    SEMICONDUCTOR DEVICE WITH FUSE AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE WITH FUSE AND METHOD OF FABRICATING THE SAME 审中-公开
    具有保险丝的半导体器件及其制造方法

    公开(公告)号:US20070102785A1

    公开(公告)日:2007-05-10

    申请号:US11557012

    申请日:2006-11-06

    申请人: Ki-Jae HUR

    发明人: Ki-Jae HUR

    IPC分类号: H01L29/00

    摘要: A semiconductor device having a fuse and a method of fabricating the same are provided. An embodiment of he semiconductor device includes a fuse pattern having a fuse conductive pattern disposed on a semiconductor substrate and a fuse capping pattern disposed on the fuse conductive pattern. An upper insulating layer is formed to cover the semiconductor substrate having the fuse pattern. A fuse window exposing the fuse pattern through the upper insulating layer is formed. A fuse spacer and a fuse window spacer are disposed on sidewalls of the fuse pattern exposed by the fuse window and sidewalls of the fuse window, respectively.

    摘要翻译: 提供了具有熔丝的半导体器件及其制造方法。 半导体器件的一个实施例包括具有设置在半导体衬底上的熔丝导电图案的熔丝图案和设置在熔丝导电图案上的熔丝封盖图案。 形成上绝缘层以覆盖具有熔丝图案的半导体衬底。 形成通过上绝缘层暴露熔丝图形的熔丝窗。 保险丝隔片和保险丝窗隔离件分别设置在由保险丝窗和保险丝窗的侧壁露出的熔丝图案的侧壁上。

    Asymmetric field effect transistor
    9.
    发明申请
    Asymmetric field effect transistor 失效
    非对称场效应晶体管

    公开(公告)号:US20070034926A1

    公开(公告)日:2007-02-15

    申请号:US11586359

    申请日:2006-10-25

    IPC分类号: H01L29/94

    摘要: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

    摘要翻译: 场效应晶体管包括形成在半导体结构上的栅堆叠下的沟道区。 场效应晶体管还包括形成有掺杂沟道区的第一侧的第一掺杂物的漏极区,并且包括形成有掺杂沟道区的第二侧的第一掺杂剂的源极区。 漏极和源极区域被非对称地掺杂,使得沟道和漏极区域之间的第一电荷载流子谱具有比沟道和源极区域之间的第二电荷载流子谱更陡峭的斜率。

    Asymmetric field effect transistor
    10.
    发明申请
    Asymmetric field effect transistor 失效
    非对称场效应晶体管

    公开(公告)号:US20050127407A1

    公开(公告)日:2005-06-16

    申请号:US11003612

    申请日:2004-12-02

    摘要: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

    摘要翻译: 场效应晶体管包括形成在半导体结构上的栅堆叠下的沟道区。 场效应晶体管还包括形成有掺杂沟道区的第一侧的第一掺杂物的漏极区,并且包括形成有掺杂沟道区的第二侧的第一掺杂剂的源极区。 漏极和源极区域被非对称地掺杂,使得沟道和漏极区域之间的第一电荷载流子谱具有比沟道和源极区域之间的第二电荷载流子谱更陡峭的斜率。