公开(公告)号：US20100093141A1

公开(公告)日：2010-04-15

申请号：US12578291

申请日：2009-10-13

申请人： Hyuck-Chai Jung ,  Jun-Hee Lim

发明人： Hyuck-Chai Jung ,  Jun-Hee Lim

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L29/66575 ,  H01L21/26513 ,  H01L21/823456 ,  H01L27/0629 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7835

摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening.

摘要翻译： 在制造晶体管的方法中，在基板上形成栅极结构。 将第一杂质注入到衬底中以在与栅极结构相邻的衬底的上部形成杂质区。 在杂质区上形成外延层。 在衬底上形成具有部分暴露外延层的开口的绝缘层。 将第二杂质注入由开口暴露的外延层的一部分。

公开(公告)号：US20080272430A1

公开(公告)日：2008-11-06

申请号：US12111120

申请日：2008-04-28

申请人： Ki-Jae Hur ,  Jun-Hee Lim ,  Hyuck-Chai Jung

发明人： Ki-Jae Hur ,  Jun-Hee Lim ,  Hyuck-Chai Jung

IPC分类号： H01L29/78

CPC分类号： H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench.

摘要翻译： 半导体器件包括限定在衬底中的有源区，有源区具有在衬底的表面下方延伸的沟槽; 沿着沟槽的底表面和下侧壁设置的杂质区，其中杂质区的上部与衬底的表面和沟槽的上部间隔开; 栅极绝缘层，沿着沟槽的内表面设置; 以及设置在沟槽中的栅电极。

公开(公告)号：US08836019B2

公开(公告)日：2014-09-16

申请号：US12591142

申请日：2009-11-10

申请人： Jun-Hee Lim ,  Hyuck-Chai Jung

发明人： Jun-Hee Lim ,  Hyuck-Chai Jung

IPC分类号： H01L29/66 ,  H01L27/108 ,  H01L21/265 ,  H01L49/02

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L27/10823 ,  H01L27/10876 ,  H01L28/90

摘要： A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.

摘要翻译： 凹槽沟道晶体管，包括晶体管的半导体器件及其制造方法，凹陷沟道晶体管包括栅极结构，第二杂质区和第一杂质区。 栅极结构可以形成在衬底上并填充凹部。 包括第一杂质的第一杂质区可以形成在与栅极结构相邻的衬底的第一上部。 包括第二杂质的第二杂质区可以形成在与栅极结构接触的基板的第二上部。 第一杂质区可围绕第二杂质区。 第一杂质具有与第二杂质不同的导电型。

公开(公告)号：US08268694B2

公开(公告)日：2012-09-18

申请号：US12578291

申请日：2009-10-13

申请人： Hyuck-Chai Jung ,  Jun-Hee Lim

发明人： Hyuck-Chai Jung ,  Jun-Hee Lim

IPC分类号： H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/26513 ,  H01L21/823456 ,  H01L27/0629 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7835

摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening.

摘要翻译： 在制造晶体管的方法中，在基板上形成栅极结构。 将第一杂质注入到衬底中以在与栅极结构相邻的衬底的上部形成杂质区。 在杂质区上形成外延层。 在衬底上形成具有部分暴露外延层的开口的绝缘层。 将第二杂质注入由开口暴露的外延层的一部分。

公开(公告)号：US20100127325A1

公开(公告)日：2010-05-27

申请号：US12591142

申请日：2009-11-10

申请人： Jun-Hee Lim ,  Hyuck-Chai Jung

发明人： Jun-Hee Lim ,  Hyuck-Chai Jung

IPC分类号： H01L27/06

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L27/10823 ,  H01L27/10876 ,  H01L28/90

摘要： A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.

摘要翻译： 提供了一种凹陷沟道晶体管，包括晶体管的半导体器件及其制造方法，凹陷沟道晶体管包括栅极结构，第二杂质区和第一杂质区。 栅极结构可以形成在衬底上并填充凹部。 包括第一杂质的第一杂质区可以形成在与栅极结构相邻的衬底的第一上部。 包括第二杂质的第二杂质区可以形成在与栅极结构接触的基板的第二上部。 第一杂质区可围绕第二杂质区。 第一杂质具有与第二杂质不同的导电型。

公开(公告)号：US20080048728A1

公开(公告)日：2008-02-28

申请号：US11845693

申请日：2007-08-27

申请人： Sang-Pyo HONG ,  Jun-Hee LIM

发明人： Sang-Pyo HONG ,  Jun-Hee LIM

IPC分类号： H03F3/45

CPC分类号： H03F3/45179 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C2207/063 ,  H03F1/38 ,  H03F2200/369 ,  H03F2203/45264 ,  H03F2203/45306 ,  H03F2203/45318

摘要： In an embodiment, a sense amplifier can perform a stable differential amplifying operation while having a high differential amplification gain. The sense amplifier comprises a current sense amplification unit, a voltage difference amplification unit, and an output stabilization unit. The current sense amplification unit receives differential input currents and generates differential output voltages corresponding to the differential input currents. The voltage difference amplification unit amplifies a voltage level difference between the differential output voltages through positive feedback using cross-coupled transistors. The output stabilization unit connects output stabilizing elements having a positive input resistance in parallel with the voltage difference amplification unit having a negative input resistance to stabilize the output of the voltage difference amplification unit.

摘要翻译： 在一个实施例中，读出放大器可以执行稳定的差分放大操作，同时具有高的差分放大增益。 读出放大器包括电流检测放大单元，电压差放大单元和输出稳定单元。 电流检测放大单元接收差分输入电流并产生对应于差分输入电流的差分输出电压。 电压差放大单元使用交叉耦合晶体管通过正反馈放大差分输出电压之间的电压电平差。 输出稳定单元将具有正输入电阻的输出稳定元件与具有负输入电阻的电压差放大单元并联，以稳定电压差放大单元的输出。

公开(公告)号：US6090682A

公开(公告)日：2000-07-18

申请号：US57563

申请日：1998-04-09

申请人： Jun Hee Lim

发明人： Jun Hee Lim

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/31

CPC分类号： H01L21/0214 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/02351 ,  H01L21/31662 ,  H01L21/76202 ,  H01L21/3143 ,  H01L21/3185

摘要： Disclosed are an isolation film of a semiconductor device and a method for fabricating the same, which prevent the isolation film from being damaged due to misalignment when forming a contact hole in a region adjacent to the isolation film, to ensure stable effective isolation distance. The isolation film of a semiconductor device includes a semiconductor substrate, a lower isolation film formed in the semiconductor substrate, and an upper isolation film formed on the lower isolation film, with a material having etching selectivity different from the lower isolation film.

摘要翻译： 公开了半导体器件的隔离膜及其制造方法，其在与隔离膜相邻的区域中形成接触孔时防止隔离膜由于未对准而损坏，以确保稳定的有效隔离距离。 半导体器件的隔离膜包括半导体衬底，形成在半导体衬底中的下部隔离膜和形成在下部隔离膜上的上部隔离膜，具有与下部隔离膜不同的蚀刻选择性的材料。

公开(公告)号：US5985711A

公开(公告)日：1999-11-16

申请号：US829469

申请日：1997-04-17

申请人： Jun Hee Lim

发明人： Jun Hee Lim

IPC分类号： H01L21/302 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

CPC分类号： H01L27/10844 ,  H01L21/76895 ,  H01L21/823425 ,  H01L27/1052

摘要： A method of fabricating a semiconductor device includes the steps of forming a plurality of gate electrodes on a first region and a second region of a substrate, the plurality of gate electrodes having cap insulating layers thereon; forming source and drain regions in the first region and the second region, the source and drain regions of the second region having an LDD structure; forming an insulating layer on the substrate including the plurality of gate electrodes; forming contact holes in the insulating layer to simultaneously expose the source and the drain regions of the first region and the cap insulating layer on the gate electrodes in the second region; selectively removing the cap insulating layer on the gate electrodes in the second region; and forming a metal line in the contact holes and on the insulating layer.

摘要翻译： 制造半导体器件的方法包括以下步骤：在衬底的第一区域和第二区域上形成多个栅电极，所述多个栅极电极在其上具有帽绝缘层; 在所述第一区域和所述第二区域中形成源极和漏极区域，所述第二区域的源极和漏极区域具有LDD结构; 在包括所述多个栅电极的所述基板上形成绝缘层; 在所述绝缘层中形成接触孔以同时暴露所述第二区域中的所述栅电极上的所述第一区域和所述帽绝缘层的源极和漏极区域; 选择性地去除第二区域中的栅电极上的帽绝缘层; 以及在接触孔和绝缘层上形成金属线。

公开(公告)号：US5780334A

公开(公告)日：1998-07-14

申请号：US730705

申请日：1996-10-11

申请人： Jun-Hee Lim ,  Mun-Mo Jeong

发明人： Jun-Hee Lim ,  Mun-Mo Jeong

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method of fabricating a capacitor of a semiconductor memory device includes the steps of: forming an interlevel insulating layer on a semiconductor substrate on which the capacitor will be formed, selectively etching a portion of the interlevel insulating layer placed on a capacitor forming portion to form a capacitor node hole, and forming a first temporary layer on the interlevel insulating layer, including a portion of the interlevel insulating layer in which the capacitor node hole is formed; forming a contact hole beneath the capacitor node hole in a capacitor contact portion; forming a conductive layer on the first temporary layer to bury the contact hole and the capacitor node hole, and then forming a second temporary layer on the conductive layer; etching back the second temporary layer through anisotropic etching process to expose the conductive layer, and to simultaneously form a temporary pillar layer inside the capacitor node hole, the temporary pillar layer being substantially surrounded by the conductive layer; removing a portion of the conductive layer placed on a portion other than the capacitor forming portion, to form a first capacitor electrode and to expose at least a portion of the first temporary layer; and removing remaining portions of the first and second temporary layers to expose an upper portion of the first capacitor electrode, forming a dielectric layer on a surface of the first capacitor electrode, and forming a second capacitor electrode on a surface of the dielectric layer.

摘要翻译： 制造半导体存储器件的电容器的方法包括以下步骤：在要形成电容器的半导体衬底上形成层间绝缘层，选择性地蚀刻位于电容器形成部分上的层间绝缘层的一部分以形成 电容器节点孔，并且在所述层间绝缘层上形成包括形成有所述电容器节点孔的所述层间绝缘层的一部分的第一临时层; 在电容器接触部分中的电容器节点孔下方形成接触孔; 在所述第一临时层上形成导电层以埋置所述接触孔和所述电容器节点孔，然后在所述导电层上形成第二临时层; 通过各向异性蚀刻工艺蚀刻第二临时层以暴露导电层，并且在电容器节点孔内同时形成临时柱层，临时柱层基本上被导电层包围; 去除放置在除电容器形成部分之外的部分上的导电层的一部分，以形成第一电容器电极并暴露第一临时层的至少一部分; 以及去除所述第一和第二临时层的剩余部分以暴露所述第一电容器电极的上部，在所述第一电容器电极的表面上形成介电层，以及在所述电介质层的表面上形成第二电容器电极。

公开(公告)号：US08981480B2

公开(公告)日：2015-03-17

申请号：US13180822

申请日：2011-07-12

申请人： Jun-Hee Lim ,  Satoru Yamada ,  Sung-Duk Hong

发明人： Jun-Hee Lim ,  Satoru Yamada ,  Sung-Duk Hong

IPC分类号： H01L29/786 ,  H01L27/108 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L21/76264 ,  H01L21/823481

摘要： A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.

摘要翻译： 半导体器件包括掩埋阱，第一和第二有源区，隔离层和低电阻区域。 掩埋阱设置在基板上并具有第一导电类型的杂质离子。 第一和第二有源区域设置在掩埋阱上，并且每个具有与第一导电类型不同的第二导电类型的杂质离子。 隔离层设置在第一和第二有源区之间。 低电阻区域设置在隔离层和衬底之间，并且具有第二导电类型的杂质离子。 低电阻区域中的杂质离子的浓度大于第一和第二活性区域中的每一个中的杂质离子的浓度。