公开(公告)号：US09201781B2

公开(公告)日：2015-12-01

申请号：US13522397

申请日：2012-02-10

申请人： Koji Asai

发明人： Koji Asai

IPC分类号： G06F12/06 ,  G06F12/02 ,  G06T1/60 ,  G06F12/00

CPC分类号： G06F12/0223 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06T1/60

摘要： In order to realize efficient memory access, addresses in the same bank in a memory are consecutively accessed. A data processing apparatus performs mapping so as to store data, which are the same data, with use of the first arrangement and the second arrangement, respectively, in different memory areas constituting a memory. When reading a portion of the data, a selecting unit selects one of the arrangements that is more efficient in accessing the portion of the data based on an address range corresponding to the portion of the data according to each arrangement, and an access control unit accesses a memory area corresponding to the selected arrangement. The data is mapped to a position different from a position of the data in terms of relative positions with respect to boundary addresses of blocks each corresponding to the same row address in the same bank.

摘要翻译： 为了实现高效的存储器访问，存储器中相同存储体中的地址被连续访问。 数据处理装置执行映射，以分别在构成存储器的不同存储区域中使用第一布置和第二布置来存储与相同数据相同的数据。 当读取数据的一部分时，选择单元根据每个布置，根据与数据部分对应的地址范围，选择更有效地访问数据的一部分，并且访问控制单元访问 对应于所选择的布置的存储区域。 数据被映射到与数据的位置不同的位置，就相对于同一行中相同行地址的块的边界地址的相对位置而言。

公开(公告)号：US08738888B2

公开(公告)日：2014-05-27

申请号：US13615983

申请日：2012-09-14

申请人： Takashi Yamada ,  Daisuke Imoto ,  Koji Asai ,  Nobuyuki Ichiguchi ,  Tetsuji Mochida

发明人： Takashi Yamada ,  Daisuke Imoto ,  Koji Asai ,  Nobuyuki Ichiguchi ,  Tetsuji Mochida

IPC分类号： G06F12/12

CPC分类号： G06F13/1668 ,  G06T1/60

摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

摘要翻译： 根据本发明的存储器控​​制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到 存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址 存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

公开(公告)号：US20130057770A1

公开(公告)日：2013-03-07

申请号：US13522397

申请日：2012-02-10

申请人： Koji Asai

发明人： Koji Asai

IPC分类号： H04N9/64

CPC分类号： G06F12/0223 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06T1/60

摘要： In order to realize efficient memory access by reducing frequency at which areas specified by different row addresses in the same bank in a memory are consecutively accessed, the data processing apparatus (10) performs mapping so as to store data (21) and data (22), which are the same data, with use of the first arrangement and the second arrangement, respectively, in different memory areas constituting a memory (20). When reading a portion of the data, a selecting unit (21) selects one of the arrangements that is more efficient in accessing the portion of the data based on an address range corresponding to the portion of the data according to each arrangement, and an access control unit (13) accesses a memory area corresponding to the selected arrangement. Here, the data (21) is mapped to a position different from a position of the data (22) in terms of relative positions with respect to boundary addresses of blocks each corresponding to the same row address in the same bank.

摘要翻译： 为了通过降低连续访问存储器中的同一个存储体中的不同行地址指定的区域的频率来实现高效的存储器访问，数据处理装置（10）执行映射以存储数据（21）和数据（22 ），其分别是在构成存储器（20）的不同存储区域中使用第一布置和第二布置的相同数据。 当读取数据的一部分时，选择单元（21）根据每个布置，基于与数据的该部分相对应的地址范围来选择更有效地访问数据的部分中的一个，以及访问 控制单元（13）访问与所选择的布置相对应的存储区域。 这里，数据（21）被映射到与数据（22）的位置不同的位置，就相对于同一行中相同行地址的块的边界地址而言的相对位置。

公开(公告)号：US20100042751A1

公开(公告)日：2010-02-18

申请号：US12522490

申请日：2008-10-24

申请人： Kouichi Ishino ,  Takashi Morimoto ,  Koji Asai

发明人： Kouichi Ishino ,  Takashi Morimoto ,  Koji Asai

IPC分类号： G06F3/00

CPC分类号： G11C7/10 ,  G06F13/1694

摘要： A semiconductor integrated circuit ensures to reserve a required memory bandwidth at low cost. A memory bandwidth monitoring unit 1210 calculates a required memory bandwidth, monitors the usage condition of the memory, and outputs the following information to a reconfiguration control unit 1120. The information is necessary to reconfigure a reconfiguration unit 1110 into a logic unit and a temporary buffer both of which are scalable depending on the usage condition. According to information, the reconfiguration control unit 1120 controls the reconfiguration unit 1110. The buffer is for storing data accessed to or from the memory by each bus master. The logic unit acts as a bus master that only uses a portion of the memory bandwidth that remains unused during the time no access request to the data storage unit 1002 issued by a bus master unit having a higher priority level is being executed.

摘要翻译： 半导体集成电路确保以低成本保留所需的存储器带宽。 存储器带宽监视单元1210计算所需的存储器带宽，监视存储器的使用状况，并将以下信息输出到重新配置控制单元1120.该信息对于将重新配置单元1110重新配置为逻辑单元和临时缓冲器 这两者都可以根据使用条件进行扩展。 根据信息，重新配置控制单元1120控制重新配置单元1110.缓冲器用于存储由每个总线主机访问或从存储器访问的数据。 逻辑单元充当总线主机，其仅在没有执行具有较高优先级的总线主机单元发出的对数据存储单元1002的访问请求的时间内仅使用保持未使用的存储器带宽的一部分。

公开(公告)号：US20100030980A1

公开(公告)日：2010-02-04

申请号：US12443598

申请日：2007-12-25

申请人： Takashi Yamada ,  Daisuke Imoto ,  Koji Asai ,  Nobuyuki Ichiguchi ,  Tetsuji Mochida

发明人： Takashi Yamada ,  Daisuke Imoto ,  Koji Asai ,  Nobuyuki Ichiguchi ,  Tetsuji Mochida

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F13/1668 ,  G06T1/60

摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

摘要翻译： 根据本发明的存储器控​​制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到 存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址 存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

公开(公告)号：US20100023736A1

公开(公告)日：2010-01-28

申请号：US12520909

申请日：2008-10-30

申请人： Takashi Morimoto ,  Shinichiro Nishioka ,  Koji Asai

发明人： Takashi Morimoto ,  Shinichiro Nishioka ,  Koji Asai

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/45

CPC分类号： H03K19/17772 ,  G06F1/24 ,  H03K19/17756 ,  H03K19/1776

摘要： The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit.

摘要翻译： 本发明提供一种可重构电路，其包括多个重新配置单元，并且改变每个重新配置单元中包括的计算处理单元的配置。 这里，每个重新配置单元还包括：计算存储单元，用于存储由计算处理单元执行的计算结果; 标记保持单元，用于保持指示是否需要计算存储单元的初始化的初始化标志; 以及初始化控制单元，其可操作以在所述计算处理单元的配置改变期间，基于由所述标志保持单元保持的初始化标志来控制所述计算存储单元的初始化。

公开(公告)号：US06444821B1

公开(公告)日：2002-09-03

申请号：US09776854

申请日：2001-02-06

申请人： Akiko Fujii ,  Mie Kubo ,  Tomoya Yamamoto ,  Jiro Shimada ,  Ryuichi Mihara ,  Hirokazu Naora ,  Koji Asai

发明人： Akiko Fujii ,  Mie Kubo ,  Tomoya Yamamoto ,  Jiro Shimada ,  Ryuichi Mihara ,  Hirokazu Naora ,  Koji Asai

IPC分类号： C07D40112

摘要： Monohydrate and trihydrate crystals of N-(2-(4-(5H-dibenzo[a,d]cyclohepten-5-ylidene)-piperidino) ethyl)-1-formyl-4-piperidinecarboxamide hydrochloride having excellent stability.

公开(公告)号：US08533429B2

公开(公告)日：2013-09-10

申请号：US13060321

申请日：2010-04-26

申请人： Masaki Maeda ,  Yorihiko Wakayama ,  Koji Asai ,  Masahiro Ishii ,  Hiroshi Amano ,  Yoshinobu Hashimoto

发明人： Masaki Maeda ,  Yorihiko Wakayama ,  Koji Asai ,  Masahiro Ishii ,  Hiroshi Amano ,  Yoshinobu Hashimoto

IPC分类号： G06F12/00

CPC分类号： G06F12/1027

摘要： A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer.

摘要翻译： 存储器访问控制单元设置有存储单元，用于存储存储一条数据，虚拟页码和所有页面的物理页码之间的对应关系的页表，以及包括用于存储的缓冲器的转换单元 对于页面的子集中的每一个，对应的虚拟页面号码和物理页面号码，以及转换处理单元，用于根据存储在缓冲器中的内容将虚拟地址转换为物理地址。

公开(公告)号：US20110161622A1

公开(公告)日：2011-06-30

申请号：US13060321

申请日：2010-04-26

申请人： Masaki Maeda ,  Yorihiko Wakayama ,  Koji Asai ,  Masahiro Ishii ,  Hiroshi Amano ,  Yoshinobu Hashimoto

发明人： Masaki Maeda ,  Yorihiko Wakayama ,  Koji Asai ,  Masahiro Ishii ,  Hiroshi Amano ,  Yoshinobu Hashimoto

IPC分类号： G06F12/10

CPC分类号： G06F12/1027

摘要： A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer. When the virtual page number of the virtual address included in the access request does not exist in the buffer, the conversion processing unit overwrites, in the buffer, (i) the virtual page number and the physical page number of a page for which a completed conversion count, indicating a number of times the virtual address of the page has been converted to the physical address, has reached a planned conversion count, with (ii) the virtual page number of the virtual address included in the access request and the physical page number corresponding, in the storage unit, to the virtual page number.

摘要翻译： 存储器访问控制单元设置有存储单元，用于存储存储一条数据，虚拟页码和所有页面的物理页码之间的对应关系的页表，以及包括用于存储的缓冲器的转换单元 对于页面的子集中的每一个，对应的虚拟页面号码和物理页面号码，以及转换处理单元，用于根据存储在缓冲器中的内容将虚拟地址转换为物理地址。 当缓冲器中不存在包含在访问请求中的虚拟地址的虚拟页面号码时，转换处理单元在缓冲器中覆盖（i）已完成的页面的虚拟页面号码和物理页面号码 指示页面的虚拟地址已被转换为物理地址的次数的转换计数已经达到计划的转换计数，其中（ii）包括在访问请求中的虚拟地址的虚拟页面号和物理页面 在存储单元中对应于虚拟页号。

公开(公告)号：US20130013879A1

公开(公告)日：2013-01-10

申请号：US13615983

申请日：2012-09-14

申请人： Takashi YAMADA ,  Daisuke IMOTO ,  Koji ASAI ,  Nobuyuki ICHIGUCHI ,  Tetsuji MOCHIDA

发明人： Takashi YAMADA ,  Daisuke IMOTO ,  Koji ASAI ,  Nobuyuki ICHIGUCHI ,  Tetsuji MOCHIDA

IPC分类号： G06F12/00

CPC分类号： G06F13/1668 ,  G06T1/60

摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

摘要翻译： 根据本发明的存储器控​​制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到 存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址 存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。