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公开(公告)号：US09201819B2
公开(公告)日：2015-12-01
申请号：US12159048
申请日：2006-07-28
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1605 , G06F13/1647 , G06F13/1673 , G09G5/001
摘要： A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
摘要翻译： 提供了一种命令处理装置和方法，用于最佳地处理从多个主机异步发出的包括多个存储体的存储装置的命令，其中每个主机交替地为存储体0和存储体1发出命令。 命令处理装置包括获取从多个主机发出的命令的缓冲器单元，仲裁所获得的命令的仲裁单元和根据仲裁向存储装置发出命令的发布单元。 仲裁单元读取在缓冲器单元中获得的多个主器件的命令，并且作为仲裁结果选择一个命令。 仲裁单元等待直到与所选择的命令相关的主机的下一个命令变得可读，并读取下一个命令。 发行单元将选择的命令和读取命令连续地发送到存储装置。
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2.发明授权Access control device, access control integrated circuit, and access control method 有权访问控制装置，访问控制集成电路和访问控制方法公开(公告)号：US07904666B2
公开(公告)日：2011-03-08
申请号：US11917574
申请日：2006-07-06
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G06F9/4887
摘要： In a device, in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. When the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.
摘要翻译： 在需要以预定速率访问的主机和需要对访问请求进行响应的处理器访问共享存储器的设备中，提高对处理器的访问请求的响应性，同时主机以预定速率的访问 与传统技术相比是有保证的。 当主机具有可用于访问共享存储器的资源时，主机以预定速率或更高速度访问共享存储器。 当以预定速率或以上执行访问时，处理器通过使用最初分配给主机的资源来访问共享存储器。
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公开(公告)号：US20070208919A1
公开(公告)日：2007-09-06
申请号：US10599832
申请日：2005-03-18
IPC分类号： G06F12/06
CPC分类号： G06F12/0207 , H04N19/423 , H04N19/43 , H04N19/433
摘要： The information processing device in the present invention includes a memory 1 which is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (13), (14), and (15) which issue access requests, and a command processing unit (11) which converts an access address that is included in the access request issued from each master. One or more of the masters access an M×N rectangular area where M and N are integers, and the command processing unit (11) converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m≦M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n≦N, become successive.
摘要翻译： 本发明的信息处理装置包括：存储器1，其是具有突发模式的DRAM，并且在连续的列地址突发传送数据，发出访问请求的主机（13），（14）和（15），以及 命令处理单元（11），其转换从每个主机发出的访问请求中包括的访问地址。 一个或多个主机访问M×N矩形区域，其中M和N为整数，并且命令处理单元（11）转换访问地址，使得在第（K + m）列处的数据的列地址，其中K和m 是第L行的整数，m <= M，第（L + n）行的第K列的数据的列地址，其中L和n是整数，n <= N成为连续的。
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公开(公告)号：US07167520B2
公开(公告)日：2007-01-23
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
IPC分类号： H04B1/66
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译： 一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。 再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。 代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小 将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。
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公开(公告)号：US08307190B2
公开(公告)日：2012-11-06
申请号：US12443598
申请日：2007-12-25
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译： 根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到 存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址 存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。
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公开(公告)号：US20090327571A1
公开(公告)日：2009-12-31
申请号：US12159048
申请日：2006-07-28
IPC分类号： G06F12/06
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1605 , G06F13/1647 , G06F13/1673 , G09G5/001
摘要： A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
摘要翻译： 提供了一种命令处理装置和方法，用于最佳地处理从多个主机异步发出的包括多个存储体的存储装置的命令，其中每个主机交替地为存储体0和存储体1发出命令。 命令处理装置包括获取从多个主机发出的命令的缓冲器单元，仲裁所获得的命令的仲裁单元和根据仲裁向存储装置发出命令的发布单元。 仲裁单元读取在缓冲器单元中获得的多个主器件的命令，并且作为仲裁结果选择一个命令。 仲裁单元等待直到与所选择的命令相关的主机的下一个命令变得可读，并读取下一个命令。 发行单元将选择的命令和读取命令连续地发送到存储装置。
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公开(公告)号：US20050238095A1
公开(公告)日：2005-10-27
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译： 一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。 再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。 代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小 将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。
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公开(公告)号：US08738888B2
公开(公告)日：2014-05-27
申请号：US13615983
申请日：2012-09-14
IPC分类号： G06F12/12
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译： 根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到 存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址 存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。
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公开(公告)号：US07852343B2
公开(公告)日：2010-12-14
申请号：US10599832
申请日：2005-03-18
IPC分类号： G09G5/39
CPC分类号： G06F12/0207 , H04N19/423 , H04N19/43 , H04N19/433
摘要： The information processing device in the present invention includes a memory 1 which is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (13), (14), and (15) which issue access requests, and a command processing unit (11) which converts an access address that is included in the access request issued from each master. One or more of the masters access an M×N rectangular area where M and N are integers, and the command processing unit (11) converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m≦M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n≦N, become successive.
摘要翻译： 本发明的信息处理装置包括：存储器1，其是具有突发模式的DRAM，并且在连续的列地址突发传送数据，发出访问请求的主机（13），（14）和（15），以及 命令处理单元（11），其转换从每个主机发出的访问请求中包括的访问地址。 一个或多个主机访问M×N矩形区域，其中M和N是整数，并且命令处理单元（11）转换访问地址，使得在（K + m）列的数据的列地址，其中K m是第L行的m和nlE; M，第（L + n）行的第K列的数据的列地址，其中L和n是整数，并且n＆nlE; N成为连续的。
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10.发明申请PROCESSOR, PROCESSING SYSTEM, DATA SHARING PROCESSING METHOD, AND INTEGRATED CIRCUIT FOR DATA SHARING PROCESSING 有权处理器，处理系统，数据共享处理方法和用于数据共享处理的集成电路公开(公告)号：US20100077156A1
公开(公告)日：2010-03-25
申请号：US12594246
申请日：2009-03-18
申请人： Tetsuji Mochida
发明人： Tetsuji Mochida
IPC分类号： G06F12/00
CPC分类号： G06F12/1072 , G06F13/16 , G06F13/368 , G06F15/167
摘要： A processing device that processes data with use of one or more data blocks shared with a plurality of external processing devices. The device includes: a processor; a shared data storage unit that stores, respectively in one or more storage areas thereof, one or more data blocks to be shared with one or more external processing devices; an output unit that outputs, when the processor makes an access request to write data in a part of one of the data blocks, a block identifier identifying the one of the data blocks, and the data pertaining to the access request; and an input unit that judges whether to share external data outputted from one of the external processing devices, based on a block identifier outputted from the one of the external processing devices, and only when judging affirmatively, causes the shared data storage unit to store the external data.
摘要翻译： 一种使用与多个外部处理装置共享的一个或多个数据块来处理数据的处理装置。 该设备包括：处理器; 分别在一个或多个存储区域中存储要与一个或多个外部处理装置共享的一个或多个数据块的共享数据存储单元; 输出单元，当所述处理器进行访问请求以在所述数据块的一个数据块的一部分中写入数据时，输出识别所述数据块中的一个的块标识符和与所述访问请求有关的数据; 以及输入单元，其基于从所述一个所述外部处理装置输出的块标识符来判断是否共享从所述外部处理装置之一输出的外部数据，并且仅当所述共享数据存储单元存储时， 外部数据。
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