公开(公告)号：US5287316A

公开(公告)日：1994-02-15

申请号：US705387

申请日：1991-05-24

申请人： Shigeo Urushidani ,  Koji Sasayama ,  Jun Nishikido

发明人： Shigeo Urushidani ,  Koji Sasayama ,  Jun Nishikido

IPC分类号： G02B6/00 ,  G02F3/00 ,  G06E1/00 ,  H04B10/00 ,  H04B10/07 ,  H04B10/29 ,  H04Q3/52 ,  G11C19/30 ,  G11C13/04

CPC分类号： G06E1/00

摘要： A FIFO buffer in which respective portions are controlled in a distributed manner is provided. In the FIFO buffer, a number of loop circuits having delay elements are provided in which respective loop circuits are connected to one another in cascade manner. Additionally provided are a number of traffic control units for controlling the signal traffic between respective neighboring loop circuits. In the case where no signal is fed back to a traffic control unit from the output side and also a new signal is transmitted thereto from the input side, the traffic control unit transmits the new signal to the loop circuit which is on the output side. In the case where any signal is fed back to a traffic control unit from the output side and also a new signal is transmitted thereto from the input side, the traffic control unit again transmits the fed-back signal to the loop circuit which is on the output side and transmits the new signal to the loop circuit which is on the input side. In the case where any signal is fed back to a traffic control means from the output side and also no signal is transmitted thereto from the input side, the traffic control means transmits again the fed-back signal to the loop circuit which is on the output side.

摘要翻译： 提供了以分布式方式控制各个部分的FIFO缓冲器。 在FIFO缓冲器中，提供了具有延迟元件的多个环路电路，其中各个环路电路以级联的方式彼此连接。 另外提供了用于控制相应的相邻回路电路之间的信号业务的多个业务控制单元。 在没有信号从输出侧反馈到交通控制单元的情况下，并且从输入侧向其发送新信号的情况下，业务控制单元将该新信号发送到在输出侧的环路电路。 在从输出侧将任何信号反馈到业务控制单元的情况下，并且从输入侧向其发送新的信号的情况下，业务控制单元再次将反馈信号发送到位于 输出侧，并将新信号发送到输入侧的环路电路。 在任何信号从输出侧反馈到业务控制装置并且也没有信号从输入侧发送到其的情况下，业务控制装置再次将反馈信号发送到在输出端上的环路电路 侧。

公开(公告)号：US5486943A

公开(公告)日：1996-01-23

申请号：US275121

申请日：1994-07-14

申请人： Koji Sasayama ,  Keishi Habara

发明人： Koji Sasayama ,  Keishi Habara

IPC分类号： H04Q11/00 ,  H04J14/00 ,  H04J4/00 ,  H04J14/08

CPC分类号： H04Q11/0001

摘要： A photonic frequency division multiplexed FIFO buffer capable of realizing a multiple input one output FIFO buffer or a one input one output FIFO buffer by using only a small number of buffers. This buffer is formed by a plurality of loop shaped optical waveguide delay lines for storing the input optical signals from the time division multiplexed input highway, which are connected in series by a plurality of 2.times.2 optical switches for selectively transferring the input optical signals among the loop shaped optical waveguide delay lines. This buffer also includes a 1.times.2 frequency channel selector, connected at a last stage of the loop shaped optical waveguide delay lines, for selectively outputting optical signals in specific frequency channels among the input optical signals stored by the last stage of the loop shaped optical waveguide delay lines as the output optical signals to the timeslots on the time division multiplexed output highway.

摘要翻译： 能够通过仅使用少量缓冲器来实现多输入一输出FIFO缓冲器或一输入一输出FIFO缓冲器的光子频分复用FIFO缓冲器。 该缓冲器由多个环形光波导延迟线形成，用于存储来自时分多路复用输入公路的输入光信号，它们通过多个2x2光开关串联连接，用于选择性地传输环路中的输入光信号 形光波导延迟线。 该缓冲器还包括连接在环形光波导延迟线的最后阶段的1x2频道选择器，用于在由环形光波导延迟的最后阶段存储的输入光信号之间选择性地输出特定频率信道中的光信号 线作为输出光信号到时分复用输出高速公路上的时隙。

公开(公告)号：US5493434A

公开(公告)日：1996-02-20

申请号：US449683

申请日：1995-05-24

申请人： Koji Sasayama ,  Keishi Habara

发明人： Koji Sasayama ,  Keishi Habara

IPC分类号： H04Q11/00 ,  H04J14/08

CPC分类号： H04Q11/0001

摘要： A photonic frequency division multiplexed FIFO buffer capable of realizing a multiple input one output FIFO buffer or a one input one output FIFO buffer by using only a small number of buffers. This buffer is formed by a plurality of loop shaped optical waveguide delay lines for storing the input optical signals from the time division multiplexed input highway, which are connected in series by a plurality of 2.times.2 optical switches for selectively transferring the input optical signals among the loop shaped optical waveguide delay lines. This buffer also includes a 1.times.2 frequency channel selector, connected at a last stage of the loop shaped optical waveguide delay lines, for selectively outputting optical signals in specific frequency channels among the input optical signals stored by the last stage of the loop shaped optical waveguide delay lines as the output optical signals to the timeslots on the time division multiplexed output highway.

公开(公告)号：US5506712A

公开(公告)日：1996-04-09

申请号：US275127

申请日：1994-07-14

申请人： Koji Sasayama ,  Kenichi Yukimatsu ,  Keishi Habara ,  Wende Zhong ,  Masato Tsukada

发明人： Koji Sasayama ,  Kenichi Yukimatsu ,  Keishi Habara ,  Wende Zhong ,  Masato Tsukada

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04Q11/00 ,  H04J14/00 ,  H04J14/08

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04Q11/0005 ,  H04L2012/5605 ,  H04L2012/5681 ,  H04Q11/0066 ,  H04Q2011/0032

摘要： A photonic frequency routing type time division highway switch which requires no conflict control at the input side, and incorporates no inherent splitting loss of the optical signal power. The switch is formed by a plurality of tunable frequency convertors for allocating frequency channels to the optical signals on the input highways at each timeslot; a frequency router for connecting the optical signals outputted from the frequency convertors to its outputs according to the frequency channels allocated to the optical signals at each timeslot; and a plurality of frequency multiplexed output buffers for outputting the optical signals outputted from the frequency router to the output highways such that a plurality of optical signals with different frequency channels which are in an identical timeslot are outputted at different timeslots.

摘要翻译： 光输入频率路由型时分高速公路交换机，不需要在输入侧进行冲突控制，不会产生光信号功率的固有分裂损耗。 开关由多个可调频率转换器形成，用于在每个时隙向输入高速公路上的光信号分配频率信道; 频率路由器，用于根据在每个时隙分配给光信号的频率信道将从频率转换器输出的光信号连接到其输出; 以及多个频率复用输出缓冲器，用于将从频率路由器输出的光信号输出到输出高速公路，使得在不同时隙输出具有相同时隙的具有不同频率信道的多个光信号。