公开(公告)号：US20080061356A1

公开(公告)日：2008-03-13

申请号：US11775596

申请日：2007-07-10

Applicant: Jae-Hwang Kim ,  Kong-Sam Jang ,  Yong-Tae Kim

Inventor： Jae-Hwang Kim ,  Kong-Sam Jang ,  Yong-Tae Kim

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/40114

Abstract: An EEPROM device is provided with an active region including a first region, a second region having a lower top surface than a top surface of the first region, and a sidewall disposed at the boundary between the first and second regions. A tunneling region of charges for a program operation and/or an erase operation is defined within the sidewall.

Abstract translation: EEPROM器件设置有有源区域，该有源区域包括第一区域，具有比第一区域的顶表面更低的顶表面的第二区域以及设置在第一和第二区域之间的边界处的侧壁。 在侧壁中限定用于编程操作和/或擦除操作的充电的隧道区域。

公开(公告)号：US07863110B2

公开(公告)日：2011-01-04

申请号：US11907994

申请日：2007-10-19

Applicant: Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

Inventor： Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

IPC: H01L21/332 ,  H01L31/119 ,  H01L23/58

CPC classification number: H01L29/861 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/1052

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract translation: 半导体器件包括在半导体衬底上限定半导体衬底中的有源区的器件隔离层，在半导体衬底的有源区中具有第一导电类型的低电压阱，第二导电类型的高电压杂质区 半导体衬底的有源区，位于低压阱上部的高电压杂质区，高电压杂质区内的第二导电类型的高浓度杂质区，与器件隔离层间隔开;以及 在器件隔离层和高浓度杂质区之间的第一导电类型的浮置杂质区，浮置杂质区是有源区的上表面的一部分。

公开(公告)号：US20080093701A1

公开(公告)日：2008-04-24

申请号：US11907994

申请日：2007-10-19

Applicant: Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

Inventor： Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

IPC: H01L29/00 ,  H01L21/761

CPC classification number: H01L29/861 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/1052

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract translation: 半导体器件包括在半导体衬底上限定半导体衬底中的有源区的器件隔离层，在半导体衬底的有源区中具有第一导电类型的低电压阱，第二导电类型的高电压杂质区 半导体衬底的有源区，位于低压阱上部的高电压杂质区，高电压杂质区内的第二导电类型的高浓度杂质区，与器件隔离层间隔开;以及 在器件隔离层和高浓度杂质区之间的第一导电类型的浮置杂质区，浮置杂质区是有源区的上表面的一部分。

公开(公告)号：US20080142869A1

公开(公告)日：2008-06-19

申请号：US11987294

申请日：2007-11-29

Applicant: Kong-Sam Jang ,  Jeong-uk Han ,  Yong-tae Kim ,  Weon-ho Park

Inventor： Kong-Sam Jang ,  Jeong-uk Han ,  Yong-tae Kim ,  Weon-ho Park

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328

Abstract: Example embodiments relate to a non-volatile memory device and a method of forming the same. A non-volatile memory device according to example embodiments may include a conductive pattern provided on the semiconductor substrate. A tunnel insulator may be provided on the conductive pattern. A memory gate structure may be provided on the semiconductor substrate so as to cover a first end of the conductive pattern. The first end may include an upward tapering, first protrusion. A select gate structure may be provided on the semiconductor substrate so as to cover the second end of the conductive pattern. The second end may include an upward tapering, second protrusion. The coverage of the first protrusion by the memory gate structure may be greater than the coverage of the second protrusion by the select gate structure.

Abstract translation: 示例性实施例涉及非易失性存储器件及其形成方法。 根据示例性实施例的非易失性存储器件可以包括设置在半导体衬底上的导电图案。 隧道绝缘体可以设置在导电图案上。 可以在半导体衬底上提供存储栅结构，以便覆盖导电图案的第一端。 第一端可包括向上逐渐变细的第一突起。 可以在半导体衬底上设置选择栅极结构，以覆盖导电图案的第二端。 第二端可以包括向上渐缩的第二突起。 通过存储器栅极结构的第一突起的覆盖可以大于通过选择栅极结构的第二突起的覆盖。