公开(公告)号：US20130010546A1

公开(公告)日：2013-01-10

申请号：US13067911

申请日：2011-07-06

申请人： Bingda B. Wang ,  Kostadin Gitchev

发明人： Bingda B. Wang ,  Kostadin Gitchev

IPC分类号： G11C8/18

CPC分类号： G11C29/022 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1066 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/023 ,  G11C29/028

摘要： A differential data strobe receiver is provided which is configured to receive a differential data strobe signal at a first strobe input and a second strobe input, wherein transitions of the differential data strobe signal indicate sample points for an associated data signal. The differential data receiver is configured to identify the transitions of the differential strobe signal by differentially comparing values of the differential strobe signal received at the first strobe input and the second strobe input. The differential data strobe receiver comprises strobe gating circuitry configured to generate a strobe gating signal, wherein the associated data signal can only be sampled in dependence on the differential data strobe signal when the strobe gating signal is asserted and strobe input termination circuitry configured selectively to provide a first termination connection for the first strobe input and a second termination connection for the second strobe input. The differential data strobe receiver is configured, prior to receiving the differential data strobe signal in association with the associated data signal, to participate in an initial gate training process to determine a gating delay used to phase align the strobe gating signal with respect to the differential data strobe signal and the strobe input termination circuitry is configured to provide an asymmetric configuration of the first termination connection and the second termination connection during the initial gate training process.

摘要翻译： 提供差分数据选通接收机，其被配置为在第一选通输入端和第二选通输入端接收差分数据选通信号，其中差分数据选通信号的转换指示相关数据信号的采样点。 差分数据接收器被配置为通过差分比较在第一选通输入端和第二选通输入端接收的差分选通信号的值来识别差分选通信号的转换。 差分数据选通接收机包括选通门控电路，其被配置为产生选通门控信号，其中相关联的数据信号只能在选通选通信号被选择性地配置选通输入终端电路时根据差分数据选通信号进行取样， 用于第一选通输入的第一终端连接和用于第二选通输入的第二终端连接。 差分数据选通接收机在接收与相关联的数据信号相关联的差分数据选通信号之前配置为参与初始门训练处理，以确定用于相位对准选通脉冲信号相对于差分 数据选通信号和选通输入终端电路被配置为在初始门训练过程期间提供第一终端连接和第二终端连接的非对称配置。

公开(公告)号：US08024690B2

公开(公告)日：2011-09-20

申请号：US12153448

申请日：2008-05-19

申请人： Kostadin Gitchev ,  Bingda Brandon Wang

发明人： Kostadin Gitchev ,  Bingda Brandon Wang

IPC分类号： G06F17/50 ,  G06F9/455 ,  H01L25/00

CPC分类号： G06F17/5077

摘要： A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The method includes the steps of defining a plurality of cells to be provided along the wide interface of the circuitry, further devices being associated with at least one of the cells, and defining the circuitry as an array of blocks formed in rows and columns, with each cell abutting one of the columns. The method includes the steps of: providing a predetermined set of tiles, each tile providing a predetermined wiring layout, and for each block, applying predetermined rules to determine one of the tiles to be used to implement that block, where the rules take into account the location of the block in the array and any association between the further devices and the cells.

摘要翻译： 提供了一种用于确定用于集成电路的互连电路中的数据路径的路由的系统，方法和计算机程序产品。 该方法包括以下步骤：定义要沿着电路的宽接口提供的多个单元，其它设备与至少一个单元相关联，并且将电路定义为以行和列形成的块阵列，其中， 每个单元格邻接其中一列。 该方法包括以下步骤：提供预定的瓦片集合，每个瓦片提供预定布线布局，并且对于每个块，应用预定规则来确定要用于实施该块的瓦片之一，其中规则考虑 阵列中的块的位置以及其他设备和单元之间的任何关联。

公开(公告)号：US20140043071A1

公开(公告)日：2014-02-13

申请号：US13571753

申请日：2012-08-10

申请人： Bingda Brandon WANG ,  Kostadin GITCHEV

发明人： Bingda Brandon WANG ,  Kostadin GITCHEV

IPC分类号： H03L7/08

CPC分类号： G06F1/30 ,  G06F1/08

摘要： An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency.

摘要翻译： 片上数据处理装置具有从供电电压的范围中选择的工作电源电压，并且具有电压电平检测电路，配置成确定工作电源电压的电平。 电压电平检测电路包括响应于参考电压变化的自适应电路。 锁相环电路被配置为从工作电源电压产生源时钟信号，以接收电压电平选择信号，以根据电压电平选择信号选择源时钟信号的目标频率，并且相位锁定 源时钟信号在目标频率上。 初始化电路被配置为在锁相环电路已经将目标频率上的源时钟信号锁相之后，根据所述工作电源电压的电平来初始化用于数据处理的片上数据处理装置。

公开(公告)号：US08680900B2

公开(公告)日：2014-03-25

申请号：US13571753

申请日：2012-08-10

申请人： Bingda Brandon Wang ,  Kostadin Gitchev

发明人： Bingda Brandon Wang ,  Kostadin Gitchev

IPC分类号： H03L7/00

CPC分类号： G06F1/30 ,  G06F1/08

摘要： An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency.

摘要翻译： 片上数据处理装置具有从供电电压的范围中选择的工作电源电压，并且具有电压电平检测电路，配置成确定工作电源电压的电平。 电压电平检测电路包括响应于参考电压变化的自适应电路。 锁相环电路被配置为从工作电源电压产生源时钟信号，以接收电压电平选择信号，以根据电压电平选择信号选择源时钟信号的目标频率，并且相位锁定 源时钟信号在目标频率上。 初始化电路被配置为在锁相环电路已经将目标频率上的源时钟信号锁相之后，根据所述工作电源电压的电平来初始化用于数据处理的片上数据处理装置。

公开(公告)号：US08638622B2

公开(公告)日：2014-01-28

申请号：US13067911

申请日：2011-07-06

申请人： Bingda B Wang ,  Kostadin Gitchev

发明人： Bingda B Wang ,  Kostadin Gitchev

IPC分类号： G11C7/00

CPC分类号： G11C29/022 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1066 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/023 ,  G11C29/028

摘要： A differential data strobe receiver is provided which is configured to receive a differential data strobe signal at a first strobe input and a second strobe input, wherein transitions of the differential data strobe signal indicate sample points for an associated data signal. The differential data receiver is configured to identify the transitions of the differential strobe signal by differentially comparing values of the differential strobe signal received at the first strobe input and the second strobe input. The differential data strobe receiver comprises strobe gating circuitry configured to generate a strobe gating signal, wherein the associated data signal can only be sampled in dependence on the differential data strobe signal when the strobe gating signal is asserted and strobe input termination circuitry configured selectively to provide a first termination connection for the first strobe input and a second termination connection for the second strobe input. The differential data strobe receiver is configured, prior to receiving the differential data strobe signal in association with the associated data signal, to participate in an initial gate training process to determine a gating delay used to phase align the strobe gating signal with respect to the differential data strobe signal and the strobe input termination circuitry is configured to provide an asymmetric configuration of the first termination connection and the second termination connection during the initial gate training process.

摘要翻译： 提供差分数据选通接收机，其被配置为在第一选通输入端和第二选通输入端接收差分数据选通信号，其中差分数据选通信号的转换指示相关数据信号的采样点。 差分数据接收器被配置为通过差分比较在第一选通输入端和第二选通输入端接收的差分选通信号的值来识别差分选通信号的转换。 差分数据选通接收机包括选通门控电路，其被配置为产生选通门控信号，其中相关联的数据信号只能在选通选通信号被选择性地配置选通输入终端电路时根据差分数据选通信号进行取样， 用于第一选通输入的第一终端连接和用于第二选通输入的第二终端连接。 差分数据选通接收机在接收与相关联的数据信号相关联的差分数据选通信号之前，被配置为参与初始门训练处理，以确定用于相位对准选通脉冲门控信号的门控延迟 数据选通信号和选通输入终端电路被配置为在初始门训练过程期间提供第一终端连接和第二终端连接的非对称配置。

公开(公告)号：US20090288056A1

公开(公告)日：2009-11-19

申请号：US12153448

申请日：2008-05-19

申请人： Kostadin Gitchev ,  Bingda Brandon Wang

发明人： Kostadin Gitchev ,  Bingda Brandon Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The interconnect circuitry on a first side provides a narrow interface for connection to a first device, and on a second side provides a wide interface for connection to a distributed plurality of further devices. Each data path is associated with one of the further devices and provides a connection through the interconnect circuitry between that associated further device and the first device. The method comprises the steps of defining a plurality of cells to be provided along the wide interface, each of the further devices being associated with at least one of the cells, and defining the interconnect circuitry as an array of blocks formed in rows and columns, with each cell abutting one of the columns. Further, the method includes the steps of providing a predetermined set of tiles, each tile providing a predetermined wiring layout, and for each block, applying predetermined rules to determine one of the tiles to be used to implement that block. The predetermined rules take into account the location of the block in the array and the association between the plurality of further devices and the plurality of cells, ensuring that each data path provided by the interconnect circuitry has the same propagation delay. By such an approach, a structured routing method is provided that uses predetermined tiles enabling a layout design for the interconnect circuitry to be readily produced whilst ensuring that the propagation delays are matched for each of the data paths within the interconnect circuitry.

摘要翻译： 提供了一种用于确定用于集成电路的互连电路中的数据路径的路由的系统，方法和计算机程序产品。 第一侧上的互连电路提供用于连接到第一设备的窄接口，并且在第二侧上提供用于连接到分布的多个另外的设备的宽接口。 每个数据路径与其他设备中的一个相关联，并通过该相关联的另外的设备和第一设备之间的互连电路提供连接。 该方法包括以下步骤：定义要沿宽接口提供的多个单元，每个其它设备与至少一个单元相关联，并将互连电路定义为以行和列形成的块阵列， 每个单元格邻接其中一列。 此外，该方法包括以下步骤：提供预定的瓦片集合，每个瓦片提供预定的布线布局，并且对于每个块，应用预定的规则来确定要用于实现该块的瓦片之一。 预定规则考虑到阵列中的块的位置以及多个另外的设备和多个小区之间的关联，确保由互连电路提供的每个数据路径具有相同的传播延迟。 通过这种方法，提供了使用预定瓦片的结构化路由方法，其使得能够容易地产生用于互连电路的布局设计，同时确保对互连电路内的每个数据路径的传播延迟进行匹配。