公开(公告)号：US08799710B2

公开(公告)日：2014-08-05

申请号：US13535676

申请日：2012-06-28

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

IPC分类号： G06F11/00

CPC分类号： G06F15/7832 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/24

摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

公开(公告)号：US20140006750A1

公开(公告)日：2014-01-02

申请号：US13602777

申请日：2012-09-04

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

IPC分类号： G06F15/76

CPC分类号： G06F15/7832 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/24

摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

摘要翻译： 三维（3-D）处理器系统包括堆叠配置的第一处理器芯片和第二处理器芯片。 第一处理器芯片包括具有第一组状态寄存器的第一处理器。 第二处理器芯片包括具有对应于第一组状态寄存器的第二组状态寄存器的第二处理器。 第一和第二处理器通过第一和第二处理器芯片之间的垂直连接连接。 模式控制电路以多种操作模式之一操作处理器系统。 在一种操作模式中，第一处理器是有效的，而第二处理器是不活动的，并且第一处理器以大于第一处理器的最大安全速度的速度操作，并且第一处理器使用第二处理器的第二组状态寄存器 第二处理器来检查第一处理器的状态。

公开(公告)号：US20140006852A1

公开(公告)日：2014-01-02

申请号：US13535676

申请日：2012-06-28

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

IPC分类号： G06F15/80 ,  G06F11/14

CPC分类号： G06F15/7832 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/24

摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

公开(公告)号：US20090055631A1

公开(公告)日：2009-02-26

申请号：US12128757

申请日：2008-05-29

申请人： William E. Burky ,  Krishnan K. Kailas ,  Balaram Sinharoy

发明人： William E. Burky ,  Krishnan K. Kailas ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3838 ,  G06F9/384

摘要： A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time.

摘要翻译： 一种用于使用多个物理寄存器文件来实现用于数字数据处理器的寄存器重命名方案的方法，所述多个物理寄存器文件用于支持来自一个或多个线程的多个指令的无序执行，所述方法包括：使用DEF表来存储 使用指令标签的多条指令之间的指令依赖性，DEF表由逻辑寄存器名称索引，并且每个逻辑寄存器包括一个条目; 使用由指令标签索引的重命名USE表来存储由多个线程使用的多组不同类型的非构造的逻辑寄存器副本共享的逻辑到物理寄存器映射信息; 使用最后一个USE表将多组不同类型的非构造的逻辑寄存器副本的数据传输到第一组架构化的注册文件中，最后的USE表由第二组重命名的物理寄存器名称索引 文件; 并在指令发送或唤醒/发出时间执行注册重命名方案。

公开(公告)号：US20080162884A1

公开(公告)日：2008-07-03

申请号：US11618948

申请日：2007-01-02

申请人： Krishnan K. Kailas ,  Ravi Nair ,  Sumedh W. Sathaye ,  Wolfram Sauer ,  John-David Wellman

发明人： Krishnan K. Kailas ,  Ravi Nair ,  Sumedh W. Sathaye ,  Wolfram Sauer ,  John-David Wellman

IPC分类号： G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857

摘要： A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a rename map of registers for each register in the schedule, and a list of register names used in the schedule. The schedule exploits instruction-level parallelism in executing out-of-order instructions. The processor core includes a schedule cache that is configured to store schedules, a shared cache configured to store both I-side and D-side cache data, and an execution resource for requesting a schedule to be executed from the schedule cache. The processor core further includes a scheduler disposed between the schedule cache and the cache. The scheduler creating the schedule using branch execution history from a branch history table to create the instructions when the schedule requested by the execution resource is not found in the schedule cache. The processor core executes the instructions according to the schedule being executed. The method includes requesting a schedule from a schedule cache. The method further includes fetching the schedule, when the schedule is found in the schedule cache; and creating the schedule, when the schedule is not found in the schedule cache. The method also includes renaming the registers in the schedule to avoid false dependencies in a processor core, mapping registers to renamed registers in the schedule, and stitching register values in and out of another schedule according to the list of register names and the rename map of registers.

摘要翻译： 呈现执行指令的处理器核心和方法，两者都利用时间表。 每个时间表包括指令序列，调度表中的第一指令的地址，调度表中的指令的原始顺序的顺序向量，调度表中每个寄存器的寄存器的重命名映射，以及 时间表中使用的寄存器名称列表。 该调度在执行无序指令时利用指令级并行性。 处理器核心包括被配置为存储调度的调度高速缓存，被配置为存储I侧和D侧缓存数据的共享高速缓存以及用于从调度高速缓存请求执行调度的执行资源。 处理器核心还包括设置在调度高速缓存和高速缓存之间的调度器。 调度器使用分支执行历史从分支历史表创建调度，以便在调度高速缓存中找不到由执行资源请求的调度时创建指令。 处理器核心根据执行的进度执行指令。 该方法包括从调度缓存请求调度。 该方法还包括当在调度高速缓存中找到调度时获取调度; 并且在调度缓存中找不到调度时创建调度。 该方法还包括重新命名调度中的寄存器，以避免处理器核心中的错误依赖性，将寄存器映射到调度表中的重命名寄存器，以及根据寄存器名称和重命名映射 注册

公开(公告)号：US08826073B2

公开(公告)日：2014-09-02

申请号：US13602777

申请日：2012-09-04

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

IPC分类号： G06F11/00

CPC分类号： G06F15/7832 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/24

摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

摘要翻译： 三维（3-D）处理器系统包括堆叠配置的第一处理器芯片和第二处理器芯片。 第一处理器芯片包括具有第一组状态寄存器的第一处理器。 第二处理器芯片包括具有对应于第一组状态寄存器的第二组状态寄存器的第二处理器。 第一和第二处理器通过第一和第二处理器芯片之间的垂直连接连接。 模式控制电路以多种操作模式之一操作处理器系统。 在一种操作模式中，第一处理器是有效的，而第二处理器是不活动的，并且第一处理器以大于第一处理器的最大安全速度的速度操作，并且第一处理器使用第二处理器的第二组状态寄存器 第二处理器来检查第一处理器的状态。

公开(公告)号：US07454597B2

公开(公告)日：2008-11-18

申请号：US11618948

申请日：2007-01-02

申请人： Krishnan K. Kailas ,  Ravi Nair ,  Sumedh W. Sathaye ,  Wolfram Sauer ,  John-David Wellman

发明人： Krishnan K. Kailas ,  Ravi Nair ,  Sumedh W. Sathaye ,  Wolfram Sauer ,  John-David Wellman

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857

摘要： A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a rename map of registers for each register in the schedule, and a list of register names used in the schedule. The schedule exploits instruction-level parallelism in executing out-of-order instructions. The processor core includes a schedule cache that is configured to store schedules, a shared cache configured to store both I-side and D-side cache data, and an execution resource for requesting a schedule to be executed from the schedule cache. The processor core further includes a scheduler disposed between the schedule cache and the cache. The scheduler creating the schedule using branch execution history from a branch history table to create the instructions when the schedule requested by the execution resource is not found in the schedule cache. The processor core executes the instructions according to the schedule being executed. The method includes requesting a schedule from a schedule cache. The method further includes fetching the schedule, when the schedule is found in the schedule cache; and creating the schedule, when the schedule is not found in the schedule cache. The method also includes renaming the registers in the schedule to avoid false dependencies in a processor core, mapping registers to renamed registers in the schedule, and stitching register values in and out of another schedule according to the list of register names and the rename map of registers.

摘要翻译： 呈现执行指令的处理器核心和方法，两者都利用时间表。 每个时间表包括指令序列，调度表中的第一指令的地址，调度表中的指令的原始顺序的顺序向量，调度表中每个寄存器的寄存器的重命名映射，以及 时间表中使用的寄存器名称列表。 该调度在执行无序指令时利用指令级并行性。 处理器核心包括被配置为存储调度的调度高速缓存，被配置为存储I侧和D侧缓存数据的共享高速缓存以及用于从调度高速缓存请求执行调度的执行资源。 处理器核心还包括设置在调度高速缓存和高速缓存之间的调度器。 调度器使用分支执行历史从分支历史表创建调度，以便在调度高速缓存中找不到由执行资源请求的调度时创建指令。 处理器核心根据执行的进度执行指令。 该方法包括从调度缓存请求调度。 该方法还包括当在调度高速缓存中找到调度时获取调度; 并且在调度缓存中找不到调度时创建调度。 该方法还包括重新命名调度中的寄存器，以避免处理器核心中的错误依赖性，将寄存器映射到调度表中的重命名寄存器，以及根据寄存器名称和重命名映射列表将寄存器值拼接到另一个调度表中。 注册

公开(公告)号：US20080016324A1

公开(公告)日：2008-01-17

申请号：US11456878

申请日：2006-07-12

申请人： William E. Burky ,  Krishnan K. Kailas ,  Balaram Sinharoy

发明人： William E. Burky ,  Krishnan K. Kailas ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3838 ,  G06F9/384

摘要： A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time.

摘要翻译： 一种用于使用多个物理寄存器文件来实现用于数字数据处理器的寄存器重命名方案的方法，所述多个物理寄存器文件用于支持来自一个或多个线程的多个指令的无序执行，所述方法包括：使用DEF表来存储 使用指令标签的多条指令之间的指令依赖性，DEF表由逻辑寄存器名称索引，并且每个逻辑寄存器包括一个条目; 使用由指令标签索引的重命名USE表来存储由多个线程使用的多组不同类型的非构造的逻辑寄存器副本共享的逻辑到物理寄存器映射信息; 使用最后一个USE表将多组不同类型的非构造的逻辑寄存器副本的数据传输到第一组架构化的注册文件中，最后的USE表由第二组重命名的物理寄存器名称索引 文件; 并在指令发送或唤醒/发出时间执行注册重命名方案。

公开(公告)号：US07506139B2

公开(公告)日：2009-03-17

申请号：US11456878

申请日：2006-07-12

申请人： William E. Burky ,  Krishnan K. Kailas ,  Balaram Sinharoy

发明人： William E. Burky ,  Krishnan K. Kailas ,  Balaram Sinharoy

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/3838 ,  G06F9/384

摘要： A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time.

摘要翻译： 一种用于使用多个物理寄存器文件来实现用于数字数据处理器的寄存器重命名方案的方法，所述多个物理寄存器文件用于支持来自一个或多个线程的多个指令的无序执行，所述方法包括：使用DEF表来存储 使用指令标签的多条指令之间的指令依赖性，DEF表由逻辑寄存器名称索引，并且每个逻辑寄存器包括一个条目; 使用由指令标签索引的重命名USE表来存储由多个线程使用的多组不同类型的非构造的逻辑寄存器副本共享的逻辑到物理寄存器映射信息; 使用最后一个USE表将多组不同类型的非构造的逻辑寄存器副本的数据传输到第一组架构化的注册文件中，最后的USE表由第二组重命名的物理寄存器名称索引 文件; 并在指令发送或唤醒/发出时间执行注册重命名方案。

公开(公告)号：US07484075B2

公开(公告)日：2009-01-27

申请号：US10320150

申请日：2002-12-16

申请人： Krishnan K. Kailas

发明人： Krishnan K. Kailas

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3012 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3891

摘要： Effective remote register file access time can be reduced in a clustered VLIW processor using partitioned register files and some additional hardware for pre-fetching remote registers. An instruction pre-fetcher and an instruction pre-decoder is used for pre-fetching and partially decoding instructions in order to pre-fetch the remote registers required for executing VLIWs at run-time, thus substantially reducing the number of inter-cluster copy instructions. The instructions (VLIWs) are scheduled taking into account the various hardware constraints such as limited inter-cluster communication bandwidth, inter-cluster communication delay, etc.

摘要翻译： 使用分区寄存器文件的集群式VLIW处理器和一些用于预取远程寄存器的附加硬件可以减少有效的远程寄存器文件访问时间。 指令预取器和指令预解码器用于预取和部分解码指令，以便在运行时预取执行VLIW所需的远程寄存器，从而大大减少了群集间复制指令的数量 。 考虑到各种硬件限制，例如有限的群集间通信带宽，群集间通信延迟等，调度指令（VLIW）。