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公开(公告)号：US20130326193A1
公开(公告)日：2013-12-05
申请号：US13485078
申请日：2012-05-31
IPC分类号： G06F9/30
CPC分类号： G06F12/1491 , G06F9/30181 , G06F9/30189 , G06F9/321 , G06F9/3802 , G06F9/3804 , G06F12/023 , G06F12/1441 , G06F2212/1044 , G06F2212/1052
摘要： Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
摘要翻译： 实施例包括处理系统，其基于存储在第一寄存器中的指令地址范围指示符来确定下一个指令获取地址是否对应于与当前特权状态相关联的第一存储器区域内的位置或与第一存储器区域相关联的第二存储器区域内的位置 不同的特权状态。 当下一个指令提取地址不在第一个存储器区域内时，只有当向不同特权状态的转换合法时才允许该指令被取出。 在另一实施例中，当为指令生成数据访问地址时，基于存储在第二寄存器中的数据地址范围指示符，确定是否允许对对应于数据访问地址的存储器位置的访问。 当当前特权状态是允许访问内存位置的权限状态时，允许访问。
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公开(公告)号：US4978927A
公开(公告)日：1990-12-18
申请号：US433260
申请日：1989-11-08
CPC分类号： H03K3/0315 , Y10S331/03
摘要： Each section (e.g., 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (FIG. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e.g., 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be disabled, thereby removing the remaining sections (106) of the oscillator from the closed loop path. The NOR gates are implemented as a differential amplifier (FIG. 5) having two transistors (610 and 612) in the input leg and one transistor (616) with its base connected to a regulated voltage (Vr) in the opposite leg. The output of the NOR gate is taken from the collectors of the input transistors. The propagation delay of the oscillator signal through the gate is minimal because, to switch the output state of the gate, only the state of one of the input transistors (610 or 612) must be changed. The short propagation delay through the gate permits high frequency operation, as well as the ability to program small incremental steps in the center frequency of the oscillator.
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公开(公告)号：US09672164B2
公开(公告)日：2017-06-06
申请号：US13485078
申请日：2012-05-31
CPC分类号： G06F12/1491 , G06F9/30181 , G06F9/30189 , G06F9/321 , G06F9/3802 , G06F9/3804 , G06F12/023 , G06F12/1441 , G06F2212/1044 , G06F2212/1052
摘要： Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
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