Adaptive recommendations of user-generated mediasets

    公开(公告)号:US09659093B1

    公开(公告)日:2017-05-23

    申请号:US13437230

    申请日:2012-04-02

    IPC分类号: G06F17/30

    CPC分类号: G06F17/30772 G06F17/30053

    摘要: This disclosure relates to adaptive recommendations for user-generated mediasets. A mediaset component provides for users to generate mediasets. A user-generated mediaset can include a user-generated playlist or a user-generated media channel. A monitoring component monitors consumption of media, e.g., by a consumer. A relatedness component determines a set of the user-generated mediasets that are related to the media consumed by the consumer. A recommendation component recommends a subset of the user-generated mediasets based on a set of criteria. A rights management component determines a set of authorizations of the consumer for respective media content associated with the set of user-generated mediasets, and takes at least one action based on the set of authorizations, e.g., updating one of the mediasets based on the set of authorizations.

    Matching video content to video bibliographic data
    3.
    发明授权
    Matching video content to video bibliographic data 有权
    将视频内容与视频书目数据进行匹配

    公开(公告)号:US08983945B1

    公开(公告)日:2015-03-17

    申请号:US13342617

    申请日:2012-01-03

    IPC分类号: G06F17/30

    CPC分类号: G06F17/3082 G06F17/30823

    摘要: The present disclosure relates to the identification of video content. In one aspect, a method includes generating a query based on bibliographic data. The method also includes obtaining a collection of resources responsive to the query, wherein one or more of the resources include text and video content. The method further includes calculating occurrence scores for the resources. A particular occurrence score for a particular resource is based at least in part on the bibliographic data matching text included in the particular resource and the text being associated with video content. The method further includes selecting one or more resources as including video content identified by the bibliographic data using the occurrence scores. The method further includes storing data associating the selected resources with the bibliographic data.

    摘要翻译: 本公开涉及视频内容的识别。 一方面,一种方法包括基于书目数据生成查询。 该方法还包括响应于查询获得资源集合,其中一个或多个资源包括文本和视频内容。 该方法还包括计算资源的发生得分。 特定资源的特定出现分数至少部分地基于包括在特定资源中的书目数据匹配文本和与视频内容相关联的文本。 该方法还包括使用发生得分将一个或多个资源选择为包括由书目数据标识的视频内容。 该方法还包括存储将所选择的资源与书目数据相关联的数据。

    High-speed low-power latches
    4.
    发明授权
    High-speed low-power latches 有权
    高速低功率锁存器

    公开(公告)号:US08970272B2

    公开(公告)日:2015-03-03

    申请号:US12121493

    申请日:2008-05-15

    摘要: A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. A third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. In another aspect, a signal generator includes at least one latch and a control circuit. The latch(es) receive a clock signal and generate an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal and generates a control signal to adjust operation of the latch(es) to obtain 50% duty cycle for the feedback signal.

    摘要翻译: 高速低功耗锁存器包括三组晶体管。 第一组晶体管基于具有非轨至轨或轨至轨电压摆幅的时钟信号选择用于锁存器的跟踪模式或保持模式。 第二组晶体管基于输入信号捕获数据值,并在跟踪模式期间提供输出信号。 第三组晶体管存储数据值,并在保持模式期间提供输出信号。 输入和输出信号具有轨到轨电压摆幅。 在另一方面,信号发生器包括至少一个锁存器和控制电路。 锁存器接收时钟信号并产生输出信号。 控制电路感测从输出信号导出的反馈信号的占空比,并产生控制信号以调整锁存器的操作,以获得反馈信号的50%占空比。

    METHOD AND SYSTEM FOR GENERATING DYNAMIC ADS WITHIN A VIDEO GAME OF A PORTABLE COMPUTING DEVICE
    5.
    发明申请
    METHOD AND SYSTEM FOR GENERATING DYNAMIC ADS WITHIN A VIDEO GAME OF A PORTABLE COMPUTING DEVICE 审中-公开
    在便携式计算设备的视频游戏中产生动态ADS的方法和系统

    公开(公告)号:US20120232988A1

    公开(公告)日:2012-09-13

    申请号:US13181389

    申请日:2011-07-12

    IPC分类号: G06Q30/00

    摘要: A method and system for generating and tracking dynamic advertisements within a program, such as a video game, running on a portable computing device (PCD) are described. The method and system include receiving a call from the program for a texture and reviewing an identifier associated with the texture. A graphics driver determines if the identifier associated with the texture matches an identifier in a texture database. The graphics driver then selects a dynamic advertisement from a texture database if the identifier associated with the texture matches the identifier in the texture database. The graphics driver issues commands to the graphics processor so that dynamic advertisement is presented on a screen display. The graphics driver then determines if a video object produced by the program blocks a portion of the dynamic advertisement present on the screen display.

    摘要翻译: 描述了在便携式计算设备(PCD)上运行的诸如视频游戏的程序内生成和跟踪动态广告的方法和系统。 该方法和系统包括从程序接收关于纹理的调用并且查看与纹理相关联的标识符。 图形驱动程序确定与纹理相关联的标识符是否与纹理数据库中的标识符匹配。 然后,如果与纹理相关联的标识符与纹理数据库中的标识符匹配,则图形驱动程序从纹理数据库中选择动态广告。 图形驱动程序向图形处理器发出命令,使得在屏幕显示上呈现动态广告。 然后,图形驱动程序确定由程序产生的视频对象是否阻挡存在于屏幕显示上的动态广告的一部分。

    LATCH STRUCTURE, FREQUENCY DIVIDER, AND METHODS FOR OPERATING SAME
    7.
    发明申请
    LATCH STRUCTURE, FREQUENCY DIVIDER, AND METHODS FOR OPERATING SAME 有权
    绞合结构,频率分配器和操作方法

    公开(公告)号:US20100073027A1

    公开(公告)日:2010-03-25

    申请号:US12552810

    申请日:2009-09-02

    IPC分类号: H03K19/094

    摘要: A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.

    摘要翻译: 闩锁包括三个电路。 当D和CK均为高电平时,当第一输入(D)和第一时钟相位(CK)均为低电平时,第一电路将第一输出(QB)驱动到第一电平,并提供高阻抗( 当对D和CK应用不同的逻辑电平时,HI-Z)。 当DB和CKB均为高电平时,第三输入(DB)和互补时钟相位(CKB)均为低电平时,第二电路将第二输出(Q)驱动到第一电平,并提供HI-Z 当DB和CKB应用不同的逻辑电平时。 当第一和第二电路在Q和QB提供HI-Z时,第三电路维持Q和QB的电压。 使用这种锁存器构造的奇数分频器可以产生50%的占空比运算,而不会将输出脉冲宽度限制为输入周期的整数倍。

    HIGH-SPEED LOW-POWER LATCHES
    8.
    发明申请
    HIGH-SPEED LOW-POWER LATCHES 有权
    高速低功率锁存器

    公开(公告)号:US20090284288A1

    公开(公告)日:2009-11-19

    申请号:US12121493

    申请日:2008-05-15

    IPC分类号: H03B19/06 H03K3/356 H03K3/017

    摘要: A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. A third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. In another aspect, a signal generator includes at least one latch and a control circuit. The latch(es) receive a clock signal and generate an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal and generates a control signal to adjust operation of the latch(es) to obtain 50% duty cycle for the feedback signal.

    摘要翻译: 高速低功耗锁存器包括三组晶体管。 第一组晶体管基于具有非轨至轨或轨至轨电压摆幅的时钟信号选择用于锁存器的跟踪模式或保持模式。 第二组晶体管基于输入信号捕获数据值,并在跟踪模式期间提供输出信号。 第三组晶体管存储数据值,并在保持模式期间提供输出信号。 输入和输出信号具有轨到轨电压摆幅。 在另一方面,信号发生器包括至少一个锁存器和控制电路。 锁存器接收时钟信号并产生输出信号。 控制电路感测从输出信号导出的反馈信号的占空比,并产生控制信号以调整锁存器的操作,以获得反馈信号的50%占空比。

    Shifter register for low power consumption application
    10.
    发明授权
    Shifter register for low power consumption application 有权
    移位寄存器用于低功耗应用

    公开(公告)号:US07522694B2

    公开(公告)日:2009-04-21

    申请号:US11985347

    申请日:2007-11-14

    IPC分类号: G11C19/00

    CPC分类号: G11C19/28

    摘要: A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.

    摘要翻译: 高压移位寄存器级,可直接接收低电压时钟信号输入而不使用时钟缓冲器。 特别地,移位寄存器级电路适于以低电压摆动时钟信号进行工作,其中级电路具有直接驱动的单个状态节点a。 这种布置允许降低功耗和更高的运行速度。