High speed trunk interface with concurrent protocol handlers
    1.
    发明授权
    High speed trunk interface with concurrent protocol handlers 失效
    高速中继接口与并发协议处理程序

    公开(公告)号:US4734908A

    公开(公告)日:1988-03-29

    申请号:US926012

    申请日:1986-10-31

    申请人: Kurt A. Hedlund

    发明人: Kurt A. Hedlund

    CPC分类号: H04L12/64

    摘要: A digital trunk interface utilizing the first protocol handler to signal the start of a packet and a second protocol handler responsive to the packet delayed to initiate the storage of the packet internally to the digital trunk interface. The digital trunk interface comprises a microprocessor and two universal synchronous asynchronous receiver transmitter (USART) circuits. One USART is directly connected to the incoming digital trunk and is utilized to inform the microprocessor when a packet is first received. The second USART receives the packet delayed by a predefined amount of time from the digital trunk. The microprocessor is responsive to the signal from the first USART that a packet has been received to perform the necessary administrative functions for receipt of the packet by the second USART.

    摘要翻译: 一个数字中继接口,利用第一协议处理器来发信号通知分组的起点,以及一个响应分组的第二协议处理器,该分组被延迟以发起分组在内部存储到数字中继接口。 数字中继接口包括微处理器和两个通用同步异步接收发射机(USART)电路。 一个USART直接连接到输入数字中继线,并且用于在首次接收到分组时通知微处理器。 第二个USART从数字中继线接收延迟了预定义时间的数据包。 微处理器响应来自第一USART的信号已经接收到分组以执行必要的管理功能,以便由第二USART接收分组。

    Asynchronous transfer mode switch architecture
    2.
    发明授权
    Asynchronous transfer mode switch architecture 失效
    异步传输模式交换架构

    公开(公告)号:US5412646A

    公开(公告)日:1995-05-02

    申请号:US242217

    申请日:1994-05-13

    IPC分类号: H04Q3/00 H04L12/56

    摘要: A high capacity packet switch is implemented using an expansion module that divides an incoming packet cell into a plurality of segments and supplies the segments, based on their sequential order, to respective ones of a plurality of concentrator units contained in the expansion module. Each concentrator unit includes a plurality of concentrator logic units and one of those logic units accepts a segment for storage based on routing information contained in the packet cell. The stored segments forming a packet cell are thereafter unloaded and recombined in proper sequence for routing to a packet switch module, which then forwards the packet cell toward its destination.

    摘要翻译: 使用扩展模块来实现高容量分组交换机,该扩展模块将进入的分组小区划分成多个分段,并且基于它们的顺序将分段提供给包含在扩展模块中的多个集中器单元中的相应的分组单元。 每个集中器单元包括多个集中器逻辑单元,并且这些逻辑单元中的一个基于分组单元中包含的路由信息​​来接受用于存储的段。 形成分组小区的所存储的段随后被卸载并以适当顺序重组,以路由到分组交换模块,分组交换模块然后将分组小区转发到其目的地。

    Multiline error detection circuit
    3.
    发明授权
    Multiline error detection circuit 失效
    多线路错误检测电路

    公开(公告)号:US4567595A

    公开(公告)日:1986-01-28

    申请号:US481058

    申请日:1983-03-31

    申请人: Kurt A. Hedlund

    发明人: Kurt A. Hedlund

    IPC分类号: G06F11/10 G06F13/28 H04L1/00

    摘要: A communication method and digital multi-customer data interface for interconnecting a number of customer terminals to a main packet switching network of a local area data transport system that provides data communication services such as interactive video text service between data service vendors and customers. The digital multi-customer interface utilizes a main processor, control circuit, and multi-customer protocol controller to implement the protocol functions for the communication of packets and control information over individual serial transmission paths. The multi-customer protocol controller comprises a control processor and a formatter circuit for synchronously communicating packets for a plurality of customer terminals via customer line units and customer lines. The control circuit handles communication of all control and status information between the main processor and the customer line units. The control circuit communicates control and status information with customer line interface units over serial transmission paths by selecting one unit at a time for transmission. Erroneous transmissions by a malfunctioning unit which has not been selected for transmission are detected by using an error generator to monitor all transmission lines and by controlling the generated error type with data from the selected unit. Unless a predefined error type is generated, an error indication is given since an erroneous transmission has occurred.

    摘要翻译: 一种通信方法和数字多用户数据接口,用于将多个客户终端互连到本地数据传输系统的主分组交换网络,该数据交换网络提供诸如数据服务供应商和客户之间的交互式视频文本服务的数据通信服务。 数字多用户接口利用主处理器,控制电路和多客户协议控制器来实现用于通过各个串行传输路径分组和控制信息的通信的协议功能。 多客户协议控制器包括控制处理器和格式化器电路,用于经由客户线路单元和客户线路同时传送多个客户终端的分组。 控制电路处理主处理器和客户线路单元之间的所有控制和状态信息的通信。 控制电路通过串行传输路径通过选择一个单元来传输控制和状态信息与客户线接口单元进行传输。 通过使用错误发生器来监测所有传输线并通过使用来自所选择的单元的数据来控制所生成的错误类型来检测未被选择用于传输的故障单元的错误传输。 除非产生了预定义的错误类型,否则发生了错误的传输。

    Hardware interface to a high-speed multiplexed link
    4.
    发明授权
    Hardware interface to a high-speed multiplexed link 失效
    硬件接口到高速多路复用链路

    公开(公告)号:US5136584A

    公开(公告)日:1992-08-04

    申请号:US551700

    申请日:1990-07-11

    申请人: Kurt A. Hedlund

    发明人: Kurt A. Hedlund

    IPC分类号: H04L12/56 H04Q11/04

    摘要: A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.

    摘要翻译: 与高速异步复用ATM电信链路的链路接口包括用于从数据帧中形成ATM信元的数据分段器,以及用于从接收的多路复用(交错)ATM信元中组装数据帧的数据汇编器和状态存储器。 一种以硬件实现的新型架构,其特征在于在数据分段器中不存在数据的中间存储和数据汇编器的流水线操作,允许链路接口以每秒数百兆比特和千兆比特的速率运行。