公开(公告)号：US20070234018A1

公开(公告)日：2007-10-04

申请号：US11278275

申请日：2006-03-31

申请人： Kurt Feiste

发明人： Kurt Feiste

IPC分类号： G06F15/00

CPC分类号： G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush count. A single step mode in the pipeline is entered in response to the flush count exceeding a threshold. The single step mode instructions are issued in serial such that an instruction is not issued for execution until a prior instruction has completed execution.

摘要翻译： 一种计算机实现的方法，装置和计算机可用程序代码，用于确保处理器流水线中的指令的前进进程。 正在接收指令。 在流水线中计数指令刷新以确定冲洗计数。 响应于冲洗计数超过阈值，输入流水线中的单步模式。 单步模式指令是以串行方式发出的，这样在一个先前的指令完成执行之前，不会执行指令执行。

公开(公告)号：US20070198814A1

公开(公告)日：2007-08-23

申请号：US11201683

申请日：2005-08-11

申请人： Christopher Abernathy ,  Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

发明人： Christopher Abernathy ,  Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3885

摘要： A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions

摘要翻译： 提供了一种用于检测和处理微处理器系统中的指令齐平的方法和装置。 提供了一种分布在数据处理系统中的所有执行单元的刷新机制。 冲洗机构不需要中央收集点将刷新信号重新分配给执行单元。 每个单元生成一个刷新向量到所有其他执行单元，用于阻止刷新指令的寄存器更新

公开(公告)号：US20070043931A1

公开(公告)日：2007-02-22

申请号：US11204414

申请日：2005-08-16

申请人： Jonathan DeMent ,  Kurt Feiste ,  Robert Philhower ,  David Shippy

发明人： Jonathan DeMent ,  Kurt Feiste ,  Robert Philhower ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3875

摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.

摘要翻译： 提出了一种用于高频失速设计的系统和方法。 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

公开(公告)号：US20070088935A1

公开(公告)日：2007-04-19

申请号：US11252410

申请日：2005-10-18

申请人： Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

发明人： Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3867

摘要： A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.

摘要翻译： 流水线处理器具有在管线的发布阶段检测寄存器访问指令的存在的电路。 在稍后阶段发生的负载丢失可能导致寄存器访问指令被标记有相关位。 寄存器访问指令在流水线下进行，当达到flush阶段时，处理器检查相关的位并刷新寄存器访问指令。

公开(公告)号：US20060224864A1

公开(公告)日：2006-10-05

申请号：US11097741

申请日：2005-03-31

申请人： Jonathan DeMent ,  Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

发明人： Jonathan DeMent ,  Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3867

摘要： A system and method for handling multi-cycle non-pipelined instruction sequencing. With the system and method, when a non-pipelined instruction is detected at an issue point, the issue logic initiates a stall that is for a minimum number of cycles that the fastest non-pipelined instruction could complete. The execution unit then takes over stalling until the non-pipelined instruction is actually completed. This allows the execution unit more time to accurately determine when the non-pipelined instruction will complete. Slightly before the execution unit has completed the instruction, it releases the stall to the issue logic. The timing of the execution unit releasing the stall signal is set so that a dependent instruction can bypass the result as soon as possible. In other words, the dependent instruction does not have to wait for the result to be written to the processor register file in order to obtain access to the result.

摘要翻译： 一种用于处理多循环非流水线指令排序的系统和方法。 利用系统和方法，当在问题点检测到非流水线的指令时，问题逻辑启动一个停止，该停顿是最快的非流水线指令可以完成的最小循环数。 然后，执行单元接管停顿，直到非流水线指令实际完成。 这允许执行单元更多的时间准确地确定何时非流水线指令将完成。 在执行单元完成指令之前，它会将该失速释放到问题逻辑。 释放停止信号的执行单元的定时被设置为使得依赖指令可以尽快绕过结果。 换句话说，依赖指令不必等待将结果写入处理器寄存器文件，以便获得对结果的访问。

公开(公告)号：US20070198812A1

公开(公告)日：2007-08-23

申请号：US11236835

申请日：2005-09-27

申请人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857

摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a main array of storage cells and an auxiliary array of storage cells coupled thereto. When a particular row of the main array includes an instruction that is not ready-to-issue, a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row of the main array may bypass the row including the stalled or not-ready-to-issue instruction. To effect this bypass, the issue queue moves the ready-to-issue instruction to an issue row of the auxiliary array for issuance to an appropriate execution unit. Out-of-order issuance of instructions to the execution units thus continues despite the stalled instruction.

摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括存储单元的主阵列和与其耦合的存储单元的辅助阵列。 当主阵列的特定行包含不能准备发出的指令时，该指令将发生停顿状态。 然而，为了防止整个问题队列和处理器停止，主阵列的另一行中的就绪指令可以绕过包括已停止或尚未准备就绪的指令的行。 为了实现此旁路，问题队列将准备就绪指令移动到辅助阵列的问题行以发布到适当的执行单元。 因此，执行单元的指令的乱序发布仍然停止。

公开(公告)号：US20070245350A1

公开(公告)日：2007-10-18

申请号：US11279775

申请日：2006-04-14

申请人： Christopher Abernathy ,  Kurt Feiste ,  Ronald Hall ,  Albert Van Norstrand

发明人： Christopher Abernathy ,  Kurt Feiste ,  Ronald Hall ,  Albert Van Norstrand

IPC分类号： G06F9/46

CPC分类号： G06F9/524

摘要： A system and method for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

摘要翻译： 提供了一种用于将处理器置于逐渐减速操作模式的系统和方法。 逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。 处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

公开(公告)号：US20070245129A1

公开(公告)日：2007-10-18

申请号：US11279777

申请日：2006-04-14

申请人： Christopher Abernathy ,  Kurt Feiste ,  Ronald Hall ,  Albert Van Norstrand

发明人： Christopher Abernathy ,  Kurt Feiste ,  Ronald Hall ,  Albert Van Norstrand

IPC分类号： G06F15/00

CPC分类号： G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861

摘要： An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

摘要翻译： 提供了一种用于将处理器置于逐渐减速操作模式的问题单元。 逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。 处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

公开(公告)号：US20070074005A1

公开(公告)日：2007-03-29

申请号：US11236838

申请日：2005-09-27

申请人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3855

摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.

摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括以行和列配置的存储单元矩阵，包括耦合到执行单元的第一行。 显示从空行到无存储单元格时，逐行发行的说明。 当指示向第一行发出时，出现未占用的单元格。 当特定行包含一个尚未准备就绪的指令时，该指令发生停顿状态。 然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。 因此，对执行单元的指令的无序发布继续进行。