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1.发明申请Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system 审中-公开用于从包括主要问题队列阵列和辅助问题队列阵列在内的问题队列发出指令的方法和装置公开(公告)号：US20070198812A1
公开(公告)日：2007-08-23
申请号：US11236835
申请日：2005-09-27
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857
摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a main array of storage cells and an auxiliary array of storage cells coupled thereto. When a particular row of the main array includes an instruction that is not ready-to-issue, a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row of the main array may bypass the row including the stalled or not-ready-to-issue instruction. To effect this bypass, the issue queue moves the ready-to-issue instruction to an issue row of the auxiliary array for issuance to an appropriate execution unit. Out-of-order issuance of instructions to the execution units thus continues despite the stalled instruction.
摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括存储单元的主阵列和与其耦合的存储单元的辅助阵列。 当主阵列的特定行包含不能准备发出的指令时，该指令将发生停顿状态。 然而，为了防止整个问题队列和处理器停止，主阵列的另一行中的就绪指令可以绕过包括已停止或尚未准备就绪的指令的行。 为了实现此旁路，问题队列将准备就绪指令移动到辅助阵列的问题行以发布到适当的执行单元。 因此，执行单元的指令的乱序发布仍然停止。
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2.发明申请Method and apparatus for issuing instructions from an issue queue in an information handling system 失效用于从信息处理系统中的发布队列发出指令的方法和装置公开(公告)号：US20070074005A1
公开(公告)日：2007-03-29
申请号：US11236838
申请日：2005-09-27
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3814 , G06F9/3838 , G06F9/3855
摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.
摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括以行和列配置的存储单元矩阵，包括耦合到执行单元的第一行。 显示从空行到无存储单元格时，逐行发行的说明。 当指示向第一行发出时，出现未占用的单元格。 当特定行包含一个尚未准备就绪的指令时，该指令发生停顿状态。 然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。 因此，对执行单元的指令的无序发布继续进行。
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公开(公告)号：US20070198814A1
公开(公告)日：2007-08-23
申请号：US11201683
申请日：2005-08-11
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/3013 , G06F9/3859 , G06F9/3863 , G06F9/3885
摘要： A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions
摘要翻译： 提供了一种用于检测和处理微处理器系统中的指令齐平的方法和装置。 提供了一种分布在数据处理系统中的所有执行单元的刷新机制。 冲洗机构不需要中央收集点将刷新信号重新分配给执行单元。 每个单元生成一个刷新向量到所有其他执行单元，用于阻止刷新指令的寄存器更新
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公开(公告)号：US20070074059A1
公开(公告)日：2007-03-29
申请号：US11236657
申请日：2005-09-27
IPC分类号： G06F1/00
CPC分类号： G06F1/3237 , G06F1/3228 , G06F1/3243 , G06F9/3867 , Y02D10/128 , Y02D10/152
摘要： A system and method for dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
摘要翻译： 提出了一种用于处理器设计中的动态功率管理的系统和方法。 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。
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5.发明申请System and method for dynamically selecting storage instruction performance scheme 审中-公开动态选择存储指令性能方案的系统和方法公开(公告)号：US20070118726A1
公开(公告)日：2007-05-24
申请号：US11284681
申请日：2005-11-22
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/3824 , G06F9/3851 , G06F9/3867
摘要： A system and method for dynamic switching between performance schemes is presented. The software program uses an instruction to indicate whether a pacing performance scheme or a flushing performance scheme is to be used. The selection by the software program is stored in a hardware register that the processor uses to determine whether the pacing or flushing performance scheme is used. After setting the performance scheme, subsequent instructions of the software program will be executed using the selected performance scheme. The pacing performance scheme preemptively stalls an instruction that might overload the queue that stores instructions for the Load/Store Unit (LSU). The flushing performance scheme flushes instructions when the LSU storage queue is overloaded and holds the thread that caused the overflow dormant until the queue is no longer full.
摘要翻译： 介绍了性能方案之间动态切换的系统和方法。 软件程序使用指令来指示是否使用起搏性能方案或冲洗性能方案。 软件程序的选择存储在硬件寄存器中，处理器用来确定是否使用起搏或冲洗性能方案。 在设置性能方案之后，将使用所选择的性能方案来执行软件程序的后续指令。 起搏性能方案会先预先停止可能使存储针对加载/存储单元（LSU）的指令的队列过载的指令。 当LSU存储队列过载时，刷新性能方案会刷新指令，并保持导致溢出休眠的线程，直到队列不再满。
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6.发明申请Queue design supporting dependency checking and issue for simd instructions within a general purpose processor 有权队列设计支持通用处理器中的simd指令的依赖关系检查和问题公开(公告)号：US20070083734A1
公开(公告)日：2007-04-12
申请号：US11204413
申请日：2005-08-16
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3885 , G06F9/3887
摘要： A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same “front-end” pipelines within an Instruction Unit. Within the shared pipelines the Instruction Unit checks the GP instructions for dependencies and resolves these dependencies. At the dispatch point within the pipelines the Instruction Unit sends valid GP instructions to the GP Unit and SIMD instructions to an SIMD issue queue. In the SIMD issue queue the Instruction Unit checks the SIMD instructions for dependencies and resolves these dependencies. Then the SIMD issue queue dispatches the SIMD instructions to the SIMD Unit. Accordingly, dependencies involving SIMD instructions do not affect GP instructions because the SIMD dependencies are checked and resolved independently.
摘要翻译： 提供了一种用于管理处理器的指令流水线内的SIMD指令和GP指令的方法，装置和计算机程序产品。 SIMD指令和GP指令在指令单元内共享相同的“前端”管道。 在共享管道中，指令单元检查GP指令的依赖关系并解决这些依赖关系。 在管线内的调度点，指令单元向GP单元发送有效的GP指令，向SIMD发出队列发送SIMD指令。 在SIMD问题队列中，指令单元检查SIMD指令的依赖性并解决这些依赖关系。 然后SIMD问题队列将SIMD指令发送到SIMD单元。 因此，涉及SIMD指令的依赖关系不会影响GP指令，因为SIMD依赖性被独立地检查和解决。
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公开(公告)号：US20060288192A1
公开(公告)日：2006-12-21
申请号：US11154158
申请日：2005-06-16
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3009 , G06F9/3802
摘要： The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the block matches the length of the latency, so the pipeline can dispatch instructions from the blocked thread after the long latency condition is resolved. In one embodiment the dispatch-block signaling instruction is a modified OR instruction and in another embodiment it is a Nop instruction. By blocking one thread at dispatch, the processor can dispatch instructions from the other threads during the block.
摘要翻译： 本发明提供一种方法，计算机程序产品和用于在多线程处理器中调度线程的线程的装置，用于线程性能的细粒度控制。 多个线程在处理器中共享流水线。 因此，一个线程上的指令的长延迟条件可以阻止所有共享流水线的线程。 调度块信令指令在发送时阻止包含长延迟条件的线程。 块的长度与延迟的长度相匹配，因此，在长时间等待条件解决之后，流水线可以从阻塞的线程中分派指令。 在一个实施例中，调度块信令指令是经修改的OR指令，在另一实施例中是Nop指令。 通过在调度时阻止一个线程，处理器可以在块期间从其他线程分派指令。
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8.发明申请SYSTEM AND METHOD FOR PLACING A PROCESSOR INTO A GRADUAL SLOW MODE OF OPERATION 有权将处理器放置在较慢的操作模式中的系统和方法公开(公告)号：US20070245350A1
公开(公告)日：2007-10-18
申请号：US11279775
申请日：2006-04-14
IPC分类号： G06F9/46
CPC分类号： G06F9/524
摘要： A system and method for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译： 提供了一种用于将处理器置于逐渐减速操作模式的系统和方法。 逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。 处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。
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9.发明申请公开(公告)号：US20070245129A1
公开(公告)日：2007-10-18
申请号：US11279777
申请日：2006-04-14
IPC分类号： G06F15/00
CPC分类号： G06F9/3867 , G06F9/30181 , G06F9/30189 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3861
摘要： An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译： 提供了一种用于将处理器置于逐渐减速操作模式的问题单元。 逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。 处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。
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10.发明申请Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines 失效通过不再需要跨不同执行管道的统一完成点来执行按顺序处理器的性能公开(公告)号：US20070022278A1
公开(公告)日：2007-01-25
申请号：US11184349
申请日：2005-07-19
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要翻译： 一种用于改善按顺序处理器的性能的方法，系统和处理器。 处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。 备用管道可以存储发给正常管道的指令的副本。 执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。 通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。 结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。
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