公开(公告)号：US20070198812A1

公开(公告)日：2007-08-23

申请号：US11236835

申请日：2005-09-27

申请人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857

摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a main array of storage cells and an auxiliary array of storage cells coupled thereto. When a particular row of the main array includes an instruction that is not ready-to-issue, a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row of the main array may bypass the row including the stalled or not-ready-to-issue instruction. To effect this bypass, the issue queue moves the ready-to-issue instruction to an issue row of the auxiliary array for issuance to an appropriate execution unit. Out-of-order issuance of instructions to the execution units thus continues despite the stalled instruction.

摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括存储单元的主阵列和与其耦合的存储单元的辅助阵列。 当主阵列的特定行包含不能准备发出的指令时，该指令将发生停顿状态。 然而，为了防止整个问题队列和处理器停止，主阵列的另一行中的就绪指令可以绕过包括已停止或尚未准备就绪的指令的行。 为了实现此旁路，问题队列将准备就绪指令移动到辅助阵列的问题行以发布到适当的执行单元。 因此，执行单元的指令的乱序发布仍然停止。

公开(公告)号：US20070074005A1

公开(公告)日：2007-03-29

申请号：US11236838

申请日：2005-09-27

申请人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3855

摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.

摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括以行和列配置的存储单元矩阵，包括耦合到执行单元的第一行。 显示从空行到无存储单元格时，逐行发行的说明。 当指示向第一行发出时，出现未占用的单元格。 当特定行包含一个尚未准备就绪的指令时，该指令发生停顿状态。 然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。 因此，对执行单元的指令的无序发布继续进行。

公开(公告)号：US20070043931A1

公开(公告)日：2007-02-22

申请号：US11204414

申请日：2005-08-16

申请人： Jonathan DeMent ,  Kurt Feiste ,  Robert Philhower ,  David Shippy

发明人： Jonathan DeMent ,  Kurt Feiste ,  Robert Philhower ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3875

摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.

摘要翻译： 提出了一种用于高频失速设计的系统和方法。 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

公开(公告)号：US20060224864A1

公开(公告)日：2006-10-05

申请号：US11097741

申请日：2005-03-31

申请人： Jonathan DeMent ,  Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

发明人： Jonathan DeMent ,  Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3867

摘要： A system and method for handling multi-cycle non-pipelined instruction sequencing. With the system and method, when a non-pipelined instruction is detected at an issue point, the issue logic initiates a stall that is for a minimum number of cycles that the fastest non-pipelined instruction could complete. The execution unit then takes over stalling until the non-pipelined instruction is actually completed. This allows the execution unit more time to accurately determine when the non-pipelined instruction will complete. Slightly before the execution unit has completed the instruction, it releases the stall to the issue logic. The timing of the execution unit releasing the stall signal is set so that a dependent instruction can bypass the result as soon as possible. In other words, the dependent instruction does not have to wait for the result to be written to the processor register file in order to obtain access to the result.

摘要翻译： 一种用于处理多循环非流水线指令排序的系统和方法。 利用系统和方法，当在问题点检测到非流水线的指令时，问题逻辑启动一个停止，该停顿是最快的非流水线指令可以完成的最小循环数。 然后，执行单元接管停顿，直到非流水线指令实际完成。 这允许执行单元更多的时间准确地确定何时非流水线指令将完成。 在执行单元完成指令之前，它会将该失速释放到问题逻辑。 释放停止信号的执行单元的定时被设置为使得依赖指令可以尽快绕过结果。 换句话说，依赖指令不必等待将结果写入处理器寄存器文件，以便获得对结果的访问。

公开(公告)号：US20070198814A1

公开(公告)日：2007-08-23

申请号：US11201683

申请日：2005-08-11

申请人： Christopher Abernathy ,  Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

发明人： Christopher Abernathy ,  Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3885

摘要： A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions

摘要翻译： 提供了一种用于检测和处理微处理器系统中的指令齐平的方法和装置。 提供了一种分布在数据处理系统中的所有执行单元的刷新机制。 冲洗机构不需要中央收集点将刷新信号重新分配给执行单元。 每个单元生成一个刷新向量到所有其他执行单元，用于阻止刷新指令的寄存器更新

公开(公告)号：US20070118726A1

公开(公告)日：2007-05-24

申请号：US11284681

申请日：2005-11-22

申请人： Christopher Abernathy ,  Jonathan DeMent ,  David Shippy ,  Albert Nordstrand

发明人： Christopher Abernathy ,  Jonathan DeMent ,  David Shippy ,  Albert Nordstrand

IPC分类号： G06F9/44 ,  G06F13/28

CPC分类号： G06F9/30181 ,  G06F9/30076 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3867

摘要： A system and method for dynamic switching between performance schemes is presented. The software program uses an instruction to indicate whether a pacing performance scheme or a flushing performance scheme is to be used. The selection by the software program is stored in a hardware register that the processor uses to determine whether the pacing or flushing performance scheme is used. After setting the performance scheme, subsequent instructions of the software program will be executed using the selected performance scheme. The pacing performance scheme preemptively stalls an instruction that might overload the queue that stores instructions for the Load/Store Unit (LSU). The flushing performance scheme flushes instructions when the LSU storage queue is overloaded and holds the thread that caused the overflow dormant until the queue is no longer full.

摘要翻译： 介绍了性能方案之间动态切换的系统和方法。 软件程序使用指令来指示是否使用起搏性能方案或冲洗性能方案。 软件程序的选择存储在硬件寄存器中，处理器用来确定是否使用起搏或冲洗性能方案。 在设置性能方案之后，将使用所选择的性能方案来执行软件程序的后续指令。 起搏性能方案会先预先停止可能使存储针对加载/存储单元（LSU）的指令的队列过载的指令。 当LSU存储队列过载时，刷新性能方案会刷新指令，并保持导致溢出休眠的线程，直到队列不再满。

公开(公告)号：US20070074059A1

公开(公告)日：2007-03-29

申请号：US11236657

申请日：2005-09-27

申请人： Christopher Abernathy ,  Jonathan DeMent ,  Ronald Hall ,  Robert Philhower ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan DeMent ,  Ronald Hall ,  Robert Philhower ,  David Shippy

IPC分类号： G06F1/00

CPC分类号： G06F1/3237 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3867 ,  Y02D10/128 ,  Y02D10/152

摘要： A system and method for dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

摘要翻译： 提出了一种用于处理器设计中的动态功率管理的系统和方法。 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。

公开(公告)号：US20070083734A1

公开(公告)日：2007-04-12

申请号：US11204413

申请日：2005-08-16

申请人： Christopher Abernathy ,  Jonathan DeMent ,  Ronald Hall ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan DeMent ,  Ronald Hall ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3885 ,  G06F9/3887

摘要： A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same “front-end” pipelines within an Instruction Unit. Within the shared pipelines the Instruction Unit checks the GP instructions for dependencies and resolves these dependencies. At the dispatch point within the pipelines the Instruction Unit sends valid GP instructions to the GP Unit and SIMD instructions to an SIMD issue queue. In the SIMD issue queue the Instruction Unit checks the SIMD instructions for dependencies and resolves these dependencies. Then the SIMD issue queue dispatches the SIMD instructions to the SIMD Unit. Accordingly, dependencies involving SIMD instructions do not affect GP instructions because the SIMD dependencies are checked and resolved independently.

摘要翻译： 提供了一种用于管理处理器的指令流水线内的SIMD指令和GP指令的方法，装置和计算机程序产品。 SIMD指令和GP指令在指令单元内共享相同的“前端”管道。 在共享管道中，指令单元检查GP指令的依赖关系并解决这些依赖关系。 在管线内的调度点，指令单元向GP单元发送有效的GP指令，向SIMD发出队列发送SIMD指令。 在SIMD问题队列中，指令单元检查SIMD指令的依赖性并解决这些依赖关系。 然后SIMD问题队列将SIMD指令发送到SIMD单元。 因此，涉及SIMD指令的依赖关系不会影响GP指令，因为SIMD依赖性被独立地检查和解决。

公开(公告)号：US20060288192A1

公开(公告)日：2006-12-21

申请号：US11154158

申请日：2005-06-16

申请人： Christopher Abernathy ,  Jonathan Dement ,  Albert Van Norstrand ,  David Shippy

发明人： Christopher Abernathy ,  Jonathan Dement ,  Albert Van Norstrand ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30079 ,  G06F9/3009 ,  G06F9/3802

摘要： The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the block matches the length of the latency, so the pipeline can dispatch instructions from the blocked thread after the long latency condition is resolved. In one embodiment the dispatch-block signaling instruction is a modified OR instruction and in another embodiment it is a Nop instruction. By blocking one thread at dispatch, the processor can dispatch instructions from the other threads during the block.

摘要翻译： 本发明提供一种方法，计算机程序产品和用于在多线程处理器中调度线程的线程的装置，用于线程性能的细粒度控制。 多个线程在处理器中共享流水线。 因此，一个线程上的指令的长延迟条件可以阻止所有共享流水线的线程。 调度块信令指令在发送时阻止包含长延迟条件的线程。 块的长度与延迟的长度相匹配，因此，在长时间等待条件解决之后，流水线可以从阻塞的线程中分派指令。 在一个实施例中，调度块信令指令是经修改的OR指令，在另一实施例中是Nop指令。 通过在调度时阻止一个线程，处理器可以在块期间从其他线程分派指令。

公开(公告)号：US20070088935A1

公开(公告)日：2007-04-19

申请号：US11252410

申请日：2005-10-18

申请人： Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

发明人： Kurt Feiste ,  David Ray ,  David Shippy ,  Albert Van Norstrand

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3867

摘要： A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.

摘要翻译： 流水线处理器具有在管线的发布阶段检测寄存器访问指令的存在的电路。 在稍后阶段发生的负载丢失可能导致寄存器访问指令被标记有相关位。 寄存器访问指令在流水线下进行，当达到flush阶段时，处理器检查相关的位并刷新寄存器访问指令。