利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.014 秒)

    OUTPUT BUFFER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING SAME
    1.
    发明申请
    OUTPUT BUFFER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING SAME 有权
    输出缓冲电路和集成电路，包括它们

    公开(公告)号：US20110267100A1

    公开(公告)日：2011-11-03

    申请号：US13179613

    申请日：2011-07-11

    申请人： Kyung-Hoi KOO

    发明人： Kyung-Hoi KOO

    IPC分类号： H03K19/003 ,  H03K19/094

    CPC分类号： H03K19/018521

    摘要： An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an electrostatic discharge (ESD) protection operation in response to the control signal.

    摘要翻译： 输出缓冲电路包括控制单元和输出驱动器。 控制单元响应于从内部电路施加的模式信号产生控制信号。 输出驱动器响应于控制信号选择性地执行驱动器操作，终止操作或静电放电（ESD）保护操作。

    ACETABULAR CUP FOR AN ARTIFICIAL HIP JOINT AND BEARING, AND ACETABULAR CUP ASSEMBLY
    2.
    发明申请
    ACETABULAR CUP FOR AN ARTIFICIAL HIP JOINT AND BEARING, AND ACETABULAR CUP ASSEMBLY 有权
    用于人工髋关节和轴承的乙烯杯和乙醇杯组件

    公开(公告)号：US20130310946A1

    公开(公告)日：2013-11-21

    申请号：US13982168

    申请日：2011-11-09

    申请人： Doo Hoon Sun ,  Yong Sik Kim ,  Kyung Hoi Koo ,  Yong-Chan Ha ,  Young-Kyun Lee

    发明人： Doo Hoon Sun ,  Yong Sik Kim ,  Kyung Hoi Koo ,  Yong-Chan Ha ,  Young-Kyun Lee

    IPC分类号： A61F2/34

    CPC分类号： A61F2/34 ,  A61F2002/30331 ,  A61F2002/30367 ,  A61F2002/30607 ,  A61F2002/3401 ,  A61F2002/3403 ,  A61F2002/3411

    摘要： An acetabular cup assembly for an artificial hip joint includes an acetabular cup including a seating recess, a female taper formed on an inner wall, protrusion recesses formed to communicate with the seating recess and insertion recesses each positioned inside a corresponding one of the protrusion recesses; and a bearing including a male taper on an outer circumference thereof, protrusions inserted into the protrusion recesses, and insertion protruding portions each formed on a corresponding one of the protrusions, the insertion protruding portions being inserted into the insertion recesses. A polyethylene bearing can be firmly fixed to the acetabular cup. When a ceramic bearing made is inserted into the acetabular cup, the area where the bearing adjoins the acetabular cup is increased, thereby preventing the ceramic bearing from being broken. Since no groove is formed along the entire circumference of the acetabular cup, the strength is increased.

    摘要翻译： 用于人造髋关节的髋臼杯组件包括髋臼杯，其包括座位凹槽，形成在内壁上的阴锥形，形成为与所述座部凹部连通的突出凹部和各自位于相应的一个突出凹部内的插入凹部; 以及在其外周上具有凸形锥形的轴承，插入到所述突起凹部中的突起以及各自形成在相应的一个突起上的插入突出部，所述插入突出部插入到所述插入凹部中。 聚乙烯轴承可以牢固地固定在髋臼杯上。 当制造的陶瓷轴承插入到髋臼杯中时，轴承邻接髋臼杯的区域增加，从而防止陶瓷轴承损坏。 由于在髋臼杯的整个圆周上没有形成凹槽，因此强度增加。

    OUTPUT BUFFER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING SAME
    3.
    发明申请
    OUTPUT BUFFER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING SAME 有权
    输出缓冲电路和集成电路，包括它们

    公开(公告)号：US20100194428A1

    公开(公告)日：2010-08-05

    申请号：US12694565

    申请日：2010-01-27

    申请人： Kyung-Hoi KOO

    发明人： Kyung-Hoi KOO

    IPC分类号： H03K19/003 ,  H03K19/094

    CPC分类号： H03K19/018521

    摘要： An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an electrostatic discharge (ESD) protection operation in response to the control signal.

    摘要翻译： 输出缓冲电路包括控制单元和输出驱动器。 控制单元响应于从内部电路施加的模式信号产生控制信号。 输出驱动器响应于控制信号选择性地执行驱动器操作，终止操作或静电放电（ESD）保护操作。

    Low voltage differential signaling receiver with a digital resistor unit and low voltage differential signaling interface system having the same
    4.
    发明授权
    Low voltage differential signaling receiver with a digital resistor unit and low voltage differential signaling interface system having the same 有权
    具有数字电阻单元的低压差分信号接收器和具有相同功能的低压差分信号接口系统

    公开(公告)号：US07443201B2

    公开(公告)日：2008-10-28

    申请号：US11432447

    申请日：2006-05-11

    申请人： Kyung-Hoi Koo

    发明人： Kyung-Hoi Koo

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0272 ,  H04L25/0292

    摘要： A low voltage differential signaling (LVDS) receiver includes a digital resistor unit configured to detect a voltage difference between a differential signal pair indicative of a digital signal, in which the digital resistor unit has a resistance value that may be varied in response to at least one control signal, a receiver unit configured to generate the digital signal in response to the detected voltage difference between the differential signal pair, and a resistance adjustment unit configured to provide the at least one control signal to the digital resistor unit to adjust the resistance value of the digital resistor unit.

    摘要翻译： 低电压差分信号（LVDS）接收器包括数字电阻器单元，其被配置为检测表示数字信号的差分信号对之间的电压差，其中数字电阻器单元具有可响应于至少 一个控制信号，接收器单元，被配置为响应于所述差分信号对之间检测到的电压差而产生数字信号，以及电阻调节单元，被配置为将所述至少一个控制信号提供给所述数字电阻器单元以调整所述电阻值 的数字电阻单元。

    DRIVER AND MEMORY CONTROLLER HAVING THE SAME
    5.
    发明申请
    DRIVER AND MEMORY CONTROLLER HAVING THE SAME 有权
    具有相同功能的驱动器和存储器控制器

    公开(公告)号：US20140313846A1

    公开(公告)日：2014-10-23

    申请号：US14134620

    申请日：2013-12-19

    申请人： Kyung-Hoi Koo

    发明人： Kyung-Hoi Koo

    IPC分类号： G11C8/08 ,  G11C8/06

    CPC分类号： G11C8/06 ,  G06F13/4072 ,  G11C5/14

    摘要： A memory controller includes a bus driver that allows the controller to support both a semiconductor memory device supporting a low power double data rate 3 (LPDDR3) transmission method and a semiconductor memory device supporting a low power double data rate 4 (LPDDR4) transmission method.

    摘要翻译： 存储器控制器包括总线驱动器，其允许控制器支持支持低功率双倍数据速率3（LPDDR3）传输方法的半导体存储器件和支持低功率双倍数据速率4（LPDDR4）传输方法的半导体存储器件。

    OUTPUT DRIVER AND ELECTRONIC SYSTEM COMPRISING SAME
    6.
    发明申请
    OUTPUT DRIVER AND ELECTRONIC SYSTEM COMPRISING SAME 有权
    输出驱动器和包含相同的电子系统

    公开(公告)号：US20120170385A1

    公开(公告)日：2012-07-05

    申请号：US13342251

    申请日：2012-01-03

    申请人： Kyung Hoi Koo

    发明人： Kyung Hoi Koo

    IPC分类号： G11C7/10 ,  G11C8/18 ,  H03K19/0175

    CPC分类号： G11C7/1057 ,  G11C7/1066 ,  H03K19/018521

    摘要： An output driver comprises a pull-up circuit that pulls up an output node to a supply voltage in N successive intervals in response to N pull-up control signals having different phases and a pull-down circuit that pulls down the output node to a ground voltage in M successive intervals in response to M pull-down control signals having different phases.

    摘要翻译： 输出驱动器包括上拉电路，其响应于具有不同相位的N个上拉控制信号和将输出节点拉低到地的下拉电路，以N个连续的间隔将输出节点拉到电源电压 响应于具有不同相位的M个下拉控制信号，M个连续间隔中的电压。

    Data strobe buffer and memory system including the same
    7.
    发明授权
    Data strobe buffer and memory system including the same 有权
    数据选通缓冲区和存储系统包括相同的

    公开(公告)号：US07804734B2

    公开(公告)日：2010-09-28

    申请号：US12193952

    申请日：2008-08-19

    申请人： Kyung-Hoi Koo ,  Jin-Ho Seo

    发明人： Kyung-Hoi Koo ,  Jin-Ho Seo

    IPC分类号： G11C8/00

    CPC分类号： G06F13/4239

    摘要： A data strobe buffer and a memory system including the data strobe buffer are provided. The data strobe buffer includes: a first input/output node; a first driver coupled to the first input/output node, the first driver configured to output a first data strobe signal to the first input/output node during a write operation; and a first receiver coupled to receive a second data strobe signal from the first input/output node and output a third data strobe signal during a read operation when the data strobe buffer is in a first or second mode, the first receiver configured to compare the second data strobe signal with a first reference voltage and output a result of the comparison as the third data strobe signal when the data strobe buffer is in the first mode, the receiver further configured to not compare the second data strobe signal with the first reference voltage when the data strobe buffer is in the second mode.

    摘要翻译： 提供数据选通缓冲器和包括数据选通缓冲器的存储器系统。 数据选通缓冲器包括：第一输入/输出节点; 耦合到所述第一输入/输出节点的第一驱动器，所述第一驱动器被配置为在写操作期间将第一数据选通信号输出到所述第一输入/输出节点; 以及第一接收器，其被耦合以在所述数据选通缓冲器处于第一或第二模式时从所述第一输入/输出节点接收第二数据选通信号并在读取操作期间输出第三数据选通信号，所述第一接收器被配置为 具有第一参考电压的第二数据选通信号，并且当数据选通缓冲器处于第一模式时，将比较结果作为第三数据选通信号输出，接收器还被配置为不将第二数据选通信号与第一参考电压进行比较 当数据选通缓冲器处于第二模式时。

    Impedance controller for semiconductor device
    8.
    发明申请
    Impedance controller for semiconductor device 有权

    公开(公告)号：US20060279345A1

    公开(公告)日：2006-12-14

    申请号：US11409756

    申请日：2006-04-24

    申请人： Kyung-Hoi Koo

    发明人： Kyung-Hoi Koo

    IPC分类号： H03L5/00

    CPC分类号： H04L25/0278

    摘要： An impedance controller includes multiple determination units for determining which of multiple candidate codes results in a best impedance match for an I/O pad of a semiconductor device. In addition, an error prevention unit of the impedance controller prevents any undesired bit pattern from causing improper operation of the impedance controller. Furthermore, the impedance controller includes a dummy transistor array for improved linearity of impedance variation.

    Output driver and electronic system comprising same
    9.
    发明授权
    Output driver and electronic system comprising same 有权
    输出驱动器和电子系统组成

    公开(公告)号：US08649228B2

    公开(公告)日：2014-02-11

    申请号：US13342251

    申请日：2012-01-03

    申请人： Kyung Hoi Koo

    发明人： Kyung Hoi Koo

    IPC分类号： G11C16/04

    CPC分类号： G11C7/1057 ,  G11C7/1066 ,  H03K19/018521

    摘要： An output driver comprises a pull-up circuit that pulls up an output node to a supply voltage in N successive intervals in response to N pull-up control signals having different phases and a pull-down circuit that pulls down the output node to a ground voltage in M successive intervals in response to M pull-down control signals having different phases.

    摘要翻译： 输出驱动器包括上拉电路，其响应于具有不同相位的N个上拉控制信号和将输出节点拉低到地的下拉电路，以N个连续的间隔将输出节点拉到电源电压 响应于具有不同相位的M个下拉控制信号，M个连续间隔中的电压。

    Impedance controller for semiconductor device
    10.
    发明授权
    Impedance controller for semiconductor device 有权
    半导体器件阻抗控制器

    公开(公告)号：US07521957B2

    公开(公告)日：2009-04-21

    申请号：US11409756

    申请日：2006-04-24

    申请人： Kyung-Hoi Koo

    发明人： Kyung-Hoi Koo

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03B1/00

    CPC分类号： H04L25/0278

    摘要： An impedance controller includes multiple determination units for determining which of multiple candidate codes results in a best impedance match for an I/O pad of a semiconductor device. In addition, an error prevention unit of the impedance controller prevents any undesired bit pattern from causing improper operation of the impedance controller. Furthermore, the impedance controller includes a dummy transistor array for improved linearity of impedance variation.

    摘要翻译： 阻抗控制器包括用于确定多个候选代码中的哪一个导致半导体器件的I / O焊盘的最佳阻抗匹配的多个确定单元。 此外，阻抗控制器的防错单元防止任何不期望的位模式导致阻抗控制器的不正确的操作。 此外，阻抗控制器包括用于改善阻抗变化的线性度的虚拟晶体管阵列。