摘要:
A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.
摘要:
In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.
摘要:
A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.
摘要:
A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.
摘要:
According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.
摘要:
In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Within data storage in the data processing system, a data structure indicates a duration of a protection window extension for each of the plurality of agents. Each protection window extension is a period following receipt of a combined response during which an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. Each of the plurality of agents is configured with a duration of a protection window extension by reference to the data structure, and at least two of the agents have protection window extensions of differing durations. The plurality of agents thereafter employ the configured protection window extensions.
摘要:
A system and method for implementing an enhanced hover state with active prefetches. According to a preferred embodiment of the present invention, a snooper in a processing unit receives a system-wide update complete operation indicating a completion of a storage-modifying operation targeting a particular address, where the storage-modifying operation results in a modified first cache line in a first cache memory. The snooper determines if a second cache memory held a second cache line associated with the particular address prior to receiving the system-wide update complete operation. If so, the snooper issues a prefetch request for a copy of the modified first cache line to replace the second cache line in the second cache memory. The snooper updates the second cache memory with a copy of the modified first cache line.
摘要:
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要:
A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.