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公开(公告)号：US06778620B1
公开(公告)日：2004-08-17
申请号：US09588599
申请日：2000-06-07
IPC分类号： H04L700
CPC分类号： H04L7/02 , H04L7/0012
摘要： A system and method of preventing metastability in conjunction with the receipt in a first clock domain of an asynchronous digital signal from a second clock domain when the first domain operates with a first clock frequency, and the second domain operates with a second clock frequency that is known within the first domain. The first domain sends information to the second domain, and includes a reference signal containing phase information known in the first domain. The information is clocked into the second domain utilizing the reference information. The second domain then sends the asynchronous digital signal to the first clock domain. A receiving unit in the first domain determines the phase information from the received signal with a known degree of maximum uncertainty that is less than one period of the reference signal. The first domain then stably reads the received asynchronous digital signal.
摘要翻译： 一种当第一域以第一时钟频率操作时，结合来自第二时钟域的异步数字信号的第一时钟域中的接收来防止亚稳态的系统和方法，并且第二域以第二时钟频率操作， 在第一个域内已知。 第一域将信息发送到第二域，并且包括包含第一域中已知的相位信息的参考信号。 使用参考信息将信息计入第二域。 然后，第二域将异步数字信号发送到第一时钟域。 第一域中的接收单元从具有已知程度的最大不确定度的接收信号确定小于参考信号的一个周期的相位信息。 第一域然后稳定地读取所接收的异步数字信号。
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2.发明授权公开(公告)号：US06457140B1
公开(公告)日：2002-09-24
申请号：US09210028
申请日：1998-12-11
IPC分类号： H02H305
CPC分类号： H04Q11/04 , H04Q2213/1305 , H04Q2213/13162 , H04Q2213/13166 , H04Q2213/13167 , H04Q2213/13292 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/1334
摘要： A fault tolerant processing system includes at least two processing planes. Each processing plane processes an input signal and generates an output signal. The system further includes plane termination logic for receiving the output signals of the processing planes to generate a non-redundant output signal. Each processing plane is provided with devices for detecting a fault in the plane, and devices for substituting, in response to detection of a fault in the plane, a signal component, referred to as control component, representing a predetermined logical state for each one of those components of the processed input signal that are affected by the detected fault. Furthermore, the plane termination logic includes devices for performing logical operations on the output signals of the planes such that, in the generation of the non-redundant output signal, unaffected signal components of a received signal override corresponding control components of another received signal.
摘要翻译： 容错处理系统包括至少两个处理平面。 每个处理平面处理输入信号并产生输出信号。 该系统还包括用于接收处理平面的输出信号以产生非冗余输出信号的平面终止逻辑。 每个处理平面设有用于检测平面中的故障的装置，以及用于响应于检测到该平面中的故障而替换被称为控制部件的信号分量的装置，该信号分量表示每一个的预定逻辑状态 处理后的输入信号的组成部分受检测到的故障影响。 此外，平面终止逻辑包括用于对平面的输出信号执行逻辑运算的装置，使得在生成非冗余输出信号时，接收信号的未受影响的信号分量覆盖另一接收信号的对应控制分量。
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公开(公告)号：US06525520B2
公开(公告)日：2003-02-25
申请号：US09840176
申请日：2001-04-24
IPC分类号： G01R2500
CPC分类号： H03K5/135 , H04J3/0688
摘要： A pulse detector detects if a clock pulse signal is in phase with a reference clock pulse signal in an efficient manner with very high accuracy. The pulse detector includes a first delay unit adapted to receive an input clock pulse signal and to delay the input clock pulse signal by a first pre-specified delay for output as output clock pulse signal, and a second delay unit adapted to delay the output clock pulse signal by a second pre-specified delay. A sampling unit is adapted to sample the input clock pulse signal and the output of the second delay unit at a sampling time defined by a reference clock pulse signal and to output the samples for phase delay indication.
摘要翻译： 脉冲检测器以非常高的精度检测时钟脉冲信号是否与参考时钟脉冲信号以有效的方式同相。 脉冲检测器包括：第一延迟单元，适于接收输入时钟脉冲信号，并将输入时钟脉冲信号延迟第一预先指定的延迟以输出作为输出时钟脉冲信号;以及第二延迟单元，适于延迟输出时钟 脉冲信号由第二预先指定的延迟。 采样单元适于在由参考时钟脉冲信号限定的采样时间采样输入时钟脉冲信号和第二延迟单元的输出，并输出采样以进行相位延迟指示。
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公开(公告)号：US6088329A
公开(公告)日：2000-07-11
申请号：US989001
申请日：1997-12-11
CPC分类号： H04Q11/04 , H04Q2213/1305 , H04Q2213/13162 , H04Q2213/13166 , H04Q2213/13167 , H04Q2213/13292 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/1334
摘要： A plurality of input signals are switched in an apparatus including redundant switching planes and hardware for receiving an output signal from each of the redundant switching planes. Each switching plane is for switching the plurality of input signals, and each switching plane includes at least two switching modules, each switching module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus. Each switching module is further connected to receive a remaining subset of the input signals from remaining switching modules on the same switching plane; and each switching module generates an output signal having components selected from the plurality of input signals. To improve performance in the event of a double fault, each switching module detects whether any of the remaining switching modules on the same switching plane are faulty. In response to any such detection, the switching module substitutes a signal representing a logical zero for those portions of the output signal that are selected to include one or more components from the faulty switching module. Also, when the means for receiving the output signal from each of the redundant switching planes detects that each of the output signals received from corresponding switching modules in the redundant switching planes is invalid; it responds by logically OR'ing the received output signals together. In this way, the likelihood of recovering a valid output signal is increased. In one embodiment of the invention, each switching module is a subrate switching module.
摘要翻译： 多个输入信号在包括冗余交换平面的设备和硬件中切换，用于从每个冗余交换平面接收输出信号。 每个切换平面用于切换多个输入信号，并且每个切换平面包括至少两个切换模块，每个切换模块被连接以直接从耦合到该设备的输入信号源接收输入信号的子集。 每个开关模块进一步连接以从相同开关平面上的剩余开关模块接收输入信号的剩余子集; 并且每个切换模块产生具有从多个输入信号中选择的分量的输出信号。 为了在双重故障的情况下提高性能，每个交换模块检测同一个交换平面上的任何剩余交换模块是否有故障。 响应任何这样的检测，切换模块将代表逻辑零的信号替换为选择的输出信号的那些部分包括来自故障切换模块的一个或多个组件。 此外，当用于接收来自每个冗余交换平面的输出信号的装置检测到从冗余交换平面中的相应交换模块接收的每个输出信号无效时; 它通过将所接收的输出信号逻辑或运算在一起来进行响应。 以这种方式，恢复有效输出信号的可能性增加。 在本发明的一个实施例中，每个交换模块是子速率交换模块。
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