公开(公告)号：US20060069537A1

公开(公告)日：2006-03-30

申请号：US10954576

申请日：2004-09-29

申请人： Lihui Cao

发明人： Lihui Cao

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The present invention provides a method for simulating noise in an integrated circuit system. According to the method disclosed herein, the present invention includes determining a plurality of peak current values, where each peak current value of the plurality of peak current values corresponds to a different voltage value. The present invention also includes graphing the plurality of peak current values as a function of voltage, and deriving a model based on the graph of the plurality of peak current values. Noise in the integrated circuit system can then be simulated based on the model.

摘要翻译： 本发明提供了一种用于模拟集成电路系统中的噪声的方法。 根据本文公开的方法，本发明包括确定多个峰值电流值，其中多个峰值电流值的每个峰值电流值对应于不同的电压值。 本发明还包括将多个峰值电流值绘制为电压的函数，并且基于多个峰值电流值的图形导出模型。 然后可以基于模型来模拟集成电路系统中的噪声。

公开(公告)号：US07705654B2

公开(公告)日：2010-04-27

申请号：US12129115

申请日：2008-05-29

申请人： Peng Rong ,  Lihui Cao

发明人： Peng Rong ,  Lihui Cao

IPC分类号： H03K17/04

CPC分类号： H03K19/0963

摘要： A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains connected to a gate of an PMOS transistor and their sources connected to the VSS rail. The drain and source of the PMOS transistor are connected to the VDD rail. None of the gates of the transistors is connected to the VDD or VSS rail. This protects the gate oxide from being damaged by ESD surge currents.

摘要翻译： 公开了具有短导通时间的快速有源DCAP单元，实现高电容密度，并且在其正常操作模式期间最小化泄漏开销。 DCAP单元具有一对PMOS晶体管，它们的漏极连接到PMOS晶体管的栅极，其源极连接到VDD导轨。 PMOS晶体管的漏极和源极连接到VSS导轨。 类似地，DCAP单元具有一对NMOS晶体管，其漏极连接到PMOS晶体管的栅极，并且其源极连接到VSS导轨。 PMOS晶体管的漏极和源极连接到VDD导轨。 晶体管的栅极都不连接到VDD或VSS导轨。 这样可以防止栅极氧化物被ESD浪涌电流损坏。

公开(公告)号：US20090295470A1

公开(公告)日：2009-12-03

申请号：US12129115

申请日：2008-05-29

申请人： Peng Rong ,  Lihui Cao

发明人： Peng Rong ,  Lihui Cao

IPC分类号： H03K5/08

CPC分类号： H03K19/0963

摘要： A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains connected to a gate of an PMOS transistor and their sources connected to the VSS rail. The drain and source of the PMOS transistor are connected to the VDD rail. None of the gates of the transistors is connected to the VDD or VSS rail. This protects the gate oxide from being damaged by ESD surge currents.

摘要翻译： 公开了一种具有短导通时间的快速有源DCAP单元，实现了高电容密度，并且在其正常操作模式期间使泄漏开销最小化。 DCAP单元具有一对PMOS晶体管，它们的漏极连接到PMOS晶体管的栅极，其源极连接到VDD导轨。 PMOS晶体管的漏极和源极连接到VSS导轨。 类似地，DCAP单元具有一对NMOS晶体管，其漏极连接到PMOS晶体管的栅极，并且其源极连接到VSS导轨。 PMOS晶体管的漏极和源极连接到VDD导轨。 晶体管的栅极都不连接到VDD或VSS导轨。 这样可以防止栅极氧化物被ESD浪涌电流损坏。

公开(公告)号：US06807656B1

公开(公告)日：2004-10-19

申请号：US10407065

申请日：2003-04-03

申请人： Lihui Cao ,  Prasad Subbarao ,  David Gradin ,  Maad Al-Dabagh ,  Weidan Li

发明人： Lihui Cao ,  Prasad Subbarao ,  David Gradin ,  Maad Al-Dabagh ,  Weidan Li

IPC分类号： G06F1750

CPC分类号： G06F17/5063 ,  G06F17/5036

摘要： A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.

摘要翻译： 公开了一种用于在ASIC设计流程期间估计去耦电容的方法。 该方法包括对一组电网结构进行预先表征，以模拟其各自的噪声行为，并将相应的噪声行为作为噪声因子存储在表中。 在用于当前设计的ASIC设计流程中，其包括至少一个预先表征的电网结构，来自该表的相应的噪声系数用于计算当前设计的去耦电容。

公开(公告)号：US20110279171A1

公开(公告)日：2011-11-17

申请号：US12778305

申请日：2010-05-12

申请人： Lihui Cao ,  Saket K. Goyal ,  Thai-Minh Nguyen

发明人： Lihui Cao ,  Saket K. Goyal ,  Thai-Minh Nguyen

IPC分类号： H01H37/76

CPC分类号： G11C7/20 ,  G11C17/16 ,  G11C2029/4402

摘要： An electrically programmable fuse controller, a method of controlling a drive voltage of an integrated circuit (IC) and an IC incorporating the controller or the method. In one embodiment, the controller includes a VID eFuse controller configured to receive and write a voltage identifier to an associated eFuse and thereafter allow the voltage identifier to be read from the eFuse and employed to set a drive voltage of an integrated circuit associated with the VID eFuse controller.

摘要翻译： 一种电可编程熔丝控制器，一种控制集成电路（IC）的驱动电压的方法和结合了该控制器或该方法的IC。 在一个实施例中，控制器包括VID eFuse控制器，其被配置为将电压标识符接收并写入相关联的eFuse，然后允许从eFuse读取电压标识符，并用于设置与VID相关联的集成电路的驱动电压 eFuse控制器。