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    Decoupling capacitance estimation and insertion flow for ASIC designs
    1.
    发明授权
    Decoupling capacitance estimation and insertion flow for ASIC designs 失效
    ASIC设计的去耦电容估计和插入流程

    公开(公告)号：US06807656B1

    公开(公告)日：2004-10-19

    申请号：US10407065

    申请日：2003-04-03

    申请人： Lihui Cao ,  Prasad Subbarao ,  David Gradin ,  Maad Al-Dabagh ,  Weidan Li

    发明人： Lihui Cao ,  Prasad Subbarao ,  David Gradin ,  Maad Al-Dabagh ,  Weidan Li

    IPC分类号： G06F1750

    CPC分类号： G06F17/5063 ,  G06F17/5036

    摘要： A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.

    摘要翻译： 公开了一种用于在ASIC设计流程期间估计去耦电容的方法。 该方法包括对一组电网结构进行预先表征，以模拟其各自的噪声行为，并将相应的噪声行为作为噪声因子存储在表中。 在用于当前设计的ASIC设计流程中，其包括至少一个预先表征的电网结构，来自该表的相应的噪声系数用于计算当前设计的去耦电容。

    Low via resistance system
    2.
    发明授权
    Low via resistance system 有权
    低通电阻系统

    公开(公告)号：US06569751B1

    公开(公告)日：2003-05-27

    申请号：US09617550

    申请日：2000-07-17

    申请人： Prabhakar P. Tripathi ,  Zhihai Wang ,  Weidan Li

    发明人： Prabhakar P. Tripathi ,  Zhihai Wang ,  Weidan Li

    IPC分类号： H01L2128

    CPC分类号： H01L21/76846 ,  C23C14/025 ,  C23C14/0641 ,  C23C14/345 ,  H01L21/2855

    摘要： A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage. The plasma within the ion metal plasma deposition chamber is energized at a second power for a second length of time, after which the substrate is removed from the ion metal plasma deposition chamber. Finally, a third liner layer of titanium nitride is deposited in a second deposition chamber, and a plug of tungsten is deposited.

    摘要翻译： 在通孔内形成金属化互连系统的方法。 钛的第一衬里层以下列方式沉积到第一厚度。 将含有通孔的基板放置在含有钛靶的离子金属等离子体沉积室内。 离子金属等离子体沉积室被抽空到第一基础压力。 在第一沉积压力下将第一氩气流引入离子金属等离子体沉积室。 衬底被偏压到第一电压。 离子金属等离子体沉积室内的等离子体在第一时间内以第一功率通电。 TixNy的第二衬里层以下列方式沉积在钛的第一内衬层的顶部上的第二厚度上。 在第二沉积压力下，将第一氮气流和第二氩气流引入离子金属等离子体沉积室。 衬底被偏压到第二电压。 离子金属等离子体沉积室内的等离子体以第二功率被施加第二时间长度，之后从离子金属等离子体沉积室中除去衬底。 最后，在第二沉积室中沉积氮化钛的第三衬里层，并沉积钨塞。

    Optimized buffering for JTAG boundary scan nets
    3.
    发明授权
    Optimized buffering for JTAG boundary scan nets 失效
    用于JTAG边界扫描网络的优化缓冲

    公开(公告)号：US07000163B1

    公开(公告)日：2006-02-14

    申请号：US10082737

    申请日：2002-02-25

    申请人： Juergen Dirks ,  Juergen K. Lahner ,  Ludger F. Johanterwage ,  Benjamin Mbouombouo ,  Human Boluki ,  Weidan Li

    发明人： Juergen Dirks ,  Juergen K. Lahner ,  Ludger F. Johanterwage ,  Benjamin Mbouombouo ,  Human Boluki ,  Weidan Li

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318572 ,  G01R31/318541

    摘要： An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.

    摘要翻译： 一种包括一组或多组边界扫描单元，一个或多个组缓冲器，一个或多个中继器缓冲器和控制器的装置。 组缓冲器可以耦合到每个边界扫描单元组。 中继器缓冲器可以与组缓冲器串联耦合。 控制器可以通过组缓冲器和中继器缓冲器耦合到边界扫描单元组。 该装置可以被配置为缓冲边界扫描单元组以反映设备周围的I / O的顺序。

    Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells
    4.
    发明授权
    Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells 有权
    低泄漏PMOS片上去耦电容电池与标准CMOS电池兼容

    公开(公告)号：US06608365B1

    公开(公告)日：2003-08-19

    申请号：US10163120

    申请日：2002-06-04

    申请人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    发明人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    IPC分类号： H01L2900

    CPC分类号： H01L27/0811 ,  H01L29/94

    摘要： An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.

    摘要翻译： 公开了与标准CMOS电池兼容的片上去耦电容器单元。 限定单元的区域的单元边界包括第一晶体管区域和第二晶体管区域。 具有n阱的PMOS晶体管形成在第一晶体管区域内。 片上去耦电容器单元还包括将n阱扩展到第二晶体管区域中的n阱延伸，从而提供与CMOS电容器单元相比具有减小的泄漏的去耦电容器单元，并且与单位面积相比增加了每单位面积的电容 一个传统的PMOS电容单元。

    On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method
    6.
    发明授权
    On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method 有权
    片上自动过程变化，电源电压变化和温度偏差（PVT）补偿方法

    公开(公告)号：US07321254B2

    公开(公告)日：2008-01-22

    申请号：US11004415

    申请日：2004-12-03

    申请人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    发明人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    IPC分类号： H03K3/01

    CPC分类号： H03K3/0315

    摘要： An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

    摘要翻译： 片上基板电压控制器，其包括连接到多路复用器的多个互连的加载环形振荡器的链，其中多路复用器被配置为平均来自互连加载的环形振荡器的所有链的输出。 多路复用器的输出端连接到诸如相位检测器的比较器。 比较器还接收来自PLL的输出，并且被配置为将多路复用器的输出与PLL的输出进行比较。 比较器的输出端连接到可控电压调节器。 可控电压调节器接收比较器的电压以及比较器的输出，并根据从比较器接收的内容施加衬底偏置。

    Method of optimizing critical path delay in an integrated circuit design
    7.
    发明授权
    Method of optimizing critical path delay in an integrated circuit design 有权
    在集成电路设计中优化关键路径延迟的方法

    公开(公告)号：US07181712B2

    公开(公告)日：2007-02-20

    申请号：US10975981

    申请日：2004-10-27

    申请人： Benjamin Mbouombouo ,  Weidan Li ,  Dana Ahrens

    发明人： Benjamin Mbouombouo ,  Weidan Li ,  Dana Ahrens

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F17/5036

    摘要： A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.

    摘要翻译： 一种用于优化集成电路设计中的关键路径延迟的方法和计算机程序产品包括以下步骤：（a）作为输入接收集成电路设计; （b）执行定时/串扰分析以识别集成电路设计中的每个时序关键网; （c）选择最佳互连配置以最小化每个时序关键网络中的路径延迟; （e）执行详细路由，其包括针对每个定时关键网络的所选择的最佳互连配置; 和（f）生成详细路由的输出。

    On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method
    8.
    发明申请
    On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method 有权
    片上自动过程变化，电源电压变化和温度偏差（PVT）补偿方法

    公开(公告)号：US20060119420A1

    公开(公告)日：2006-06-08

    申请号：US11004415

    申请日：2004-12-03

    申请人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    发明人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    IPC分类号： G05F1/10

    CPC分类号： H03K3/0315

    摘要： An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

    摘要翻译： 片上基板电压控制器，其包括连接到多路复用器的多个互连的加载环形振荡器的链，其中多路复用器被配置为平均来自互连加载的环形振荡器的所有链的输出。 多路复用器的输出端连接到诸如相位检测器的比较器。 比较器还接收来自PLL的输出，并且被配置为将多路复用器的输出与PLL的输出进行比较。 比较器的输出端连接到可控电压调节器。 可控电压调节器接收比较器的电压以及比较器的输出，并根据从比较器接收的内容施加衬底偏置。

    Low via resistance system
    9.
    发明授权
    Low via resistance system 有权
    低通电阻系统

    公开(公告)号：US06893962B2

    公开(公告)日：2005-05-17

    申请号：US10400252

    申请日：2003-03-27

    申请人： Prabhakar P. Tripathi ,  Zhihai Wang ,  Weidan Li

    发明人： Prabhakar P. Tripathi ,  Zhihai Wang ,  Weidan Li

    IPC分类号： C23C14/02 ,  C23C14/06 ,  C23C14/34 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44

    CPC分类号： H01L21/76846 ,  C23C14/025 ,  C23C14/0641 ,  C23C14/345 ,  H01L21/2855

    摘要： A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage. The plasma within the ion metal plasma deposition chamber is energized at a second power for a second length of time, after which the substrate is removed from the ion metal plasma deposition chamber. Finally, a third liner layer of titanium nitride is deposited in a second deposition chamber, and a plug of tungsten is deposited.

    摘要翻译： 在通孔内形成金属化互连系统的方法。 钛的第一衬里层以下列方式沉积到第一厚度。 将含有通孔的基板放置在含有钛靶的离子金属等离子体沉积室内。 将离子金属等离子体沉积室抽真空至第一基础压力。 在第一沉积压力下将第一氩气流引入离子金属等离子体沉积室。 衬底被偏压到第一电压。 离子金属等离子体沉积室内的等离子体在第一时间内以第一功率通电。 以下列方式将第二衬垫层的Ti x N y Y n沉积到钛的第一内衬层的顶部上的第二厚度。 在第二沉积压力下，将第一氮气流和第二氩气流引入离子金属等离子体沉积室。 衬底被偏压到第二电压。 离子金属等离子体沉积室内的等离子体以第二功率被施加第二时间长度，之后从离子金属等离子体沉积室中除去衬底。 最后，在第二沉积室中沉积氮化钛的第三衬里层，并沉积钨塞。

    Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure
    10.
    发明授权
    Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure 有权
    用于CMP去除多余沟槽或通过填充金属的方法，其抑制在集成电路结构的氧化物表面上形成凹陷区域

    公开(公告)号：US06391768B1

    公开(公告)日：2002-05-21

    申请号：US09703616

    申请日：2000-10-30

    申请人： Dawn M. Lee ,  Jayanthi Pallinti ,  Weidan Li ,  Ming-Yi Lee

    发明人： Dawn M. Lee ,  Jayanthi Pallinti ,  Weidan Li ,  Ming-Yi Lee

    IPC分类号： H01L214763

    CPC分类号： H01L21/7684

    摘要： A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer. Trenches and/or vias are formed through the ARC layer and the oxide dielectric layer. These trenches and/or vias are then filled by depositing at least one metal layer over the ARC layer. Excess trench and/or via filler metal is then removed from the top surface of the ARC layer by subjecting the metal to a CMP step which is selective to the ARC layer, thereby permitting the ARC layer to function as a CMP stop layer which protects the underlying oxide dielectric layer from exposure to the CMP process. Since the ARC layer has a lower etch rate, in the CMP process to remove metal, than does the oxide dielectric layer, the formation of dished or concave regions in the surface is inhibited, including those regions where the trenches and/or vias are closely spaced apart.

    摘要翻译： 公开了一种用于在填充之后通过化学机械抛光（CMP）对集成电路结构进行平面化的工艺，其中至少一个金属，形成在集成电路结构上的氧化硅层中的多个沟槽和/或通孔。 在CMP工艺期间，能够阻止在氧化硅表面上形成凹面部分的工艺，其中所述沟槽和/或通孔紧密间隔开的区域中，包括在集成的 电路结构，能够在CMP工艺中用作去除金属的停止层的介电材料的抗反射涂层（ARC）层; 并且使用该ARC层作为停止层来辅助去除用于填充形成在氧化物层中的沟槽和/或通孔的多余金属。 选择用于ARC层的特定材料在CMP工艺中应该具有比底层氧化物介电层更低的去除金属的蚀刻速率。 通过ARC层和氧化物介电层形成沟槽和/或通孔。 然后通过在ARC层上沉积至少一个金属层来填充这些沟槽和/或通孔。 然后通过对金属进行对ARC层有选择性的CMP步骤，从ARC层的顶表面去除过量的沟槽和/或通孔填充金属，从而允许ARC层用作CMP停止层，其保护 潜在的氧化物介电层暴露于CMP工艺。 由于ARC层具有较低的蚀刻速率，所以在除去金属的CMP工艺中，与氧化物电介质层相比，抑制了表面上的凹陷或凹陷区域的形成，包括沟槽和/或通孔密切的区域 间隔开