公开(公告)号：US07290089B2

公开(公告)日：2007-10-30

申请号：US10270753

申请日：2002-10-15

申请人： Sivagnanam Parthasarathy ,  Andrew Cofler ,  Lionel Chaverot

发明人： Sivagnanam Parthasarathy ,  Andrew Cofler ,  Lionel Chaverot

IPC分类号： G06F12/00

CPC分类号： G06F9/381 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3875 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1028 ,  Y02D10/13

摘要： For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

摘要翻译： 对于不会产生显着性能损失（如执行硬件循环）的指令集，处理器自动和动态切换到流水线的两周期访问关联的关联高速缓存而不是单周期访问。 涉及多个周期的访问使用更少的功率，因为​​只有高速缓存中的命中方式被访问，而不是索引的高速缓存行内的所有方式。 为了保持性能，在所有剩余指令中使用单周期高速缓存访​​问。 此外，在硬件环路内的指令集合完全适合预取缓冲器的情况下，高速缓存子系统对于硬件循环的任何剩余迭代而空闲以进一步降低功耗。