公开(公告)号：US07151576B2

公开(公告)日：2006-12-19

申请号：US11140848

申请日：2005-05-31

申请人： Louis F. Coffin, III

发明人： Louis F. Coffin, III

IPC分类号： H04N5/40 ,  H04N5/455 ,  H04N9/77

CPC分类号： H04N11/004

摘要： A luminance component of a video signal is modulated in a first frequency band. A first chrominance component of the video signal is modulated in a second frequency band and is mixed with an audio component. A second chrominance component of the video signal is modulated in a third frequency band. The modulated luminance component, the first modulated chrominance component, and the second modulated chrominance component are then transmitted across a communication link.

摘要翻译： 在第一频带中调制视频信号的亮度分量。 视频信号的第一色度分量被调制在第二频带中并与音频分量混合。 在第三频带中调制视频信号的第二色度分量。 调制亮度分量，第一调制色度分量和第二调制色度分量然后通过通信链路传输。

公开(公告)号：US5987579A

公开(公告)日：1999-11-16

申请号：US825404

申请日：1997-03-27

申请人： Satyanarayana Nishtala ,  Zahir Ebrahim ,  William C. Van Loo ,  Raymond Ng ,  Louis F. Coffin, III

发明人： Satyanarayana Nishtala ,  Zahir Ebrahim ,  William C. Van Loo ,  Raymond Ng ,  Louis F. Coffin, III

IPC分类号： G06F13/16 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0822 ,  G06F12/0884

摘要： In a computer system including a packet-switched bus, a method for requesting transactions such that memory accesses are initiated quickly. A master transmits a first portion of a transaction request packet having multiple portion. A memory controller receives the first portion of the transaction request, which includes a row address portion of a memory address. The memory controller initiates a memory access by applying a row address strobe signal to the row of the memory location in response to receiving the first portion of the request packet, and the master transmits any remaining portion of the transaction request. After the full memory address has been received, it is determined whether data stored at the memory location is to be read from a source other than the memory location. The memory controller aborts the memory access by inhibiting assertion of a column access strobe signal to the memory location if the data is to be read from a source other than the memory location.

摘要翻译： 在包括分组交换总线的计算机系统中，用于请求事务的方法使得快速启动存储器访问。 主设备发送具有多个部分的事务请求分组的第一部分。 存储器控制器接收事务请求的第一部分，其包括存储器地址的行地址部分。 响应于接收到请求分组的第一部分，存储器控制器通过将行地址选通信号施加到存储器位置的行来启动存储器访问，并且主机传输事务请求的任何剩余部分。 在接收到完整存储器地址之后，确定存储在存储器位置的数据是否要从存储器位置以外的源读取。 如果要从除存储器位置之外的源读取数据，则存储器控制器通过禁止对存储器位置的列存取选通信号的断言来中止存储器访问。

公开(公告)号：US5905998A

公开(公告)日：1999-05-18

申请号：US858792

申请日：1997-05-19

申请人： Zahir Ebrahim ,  Satyanarayana Nishtala ,  William C. Van Loo ,  Kevin Normoyle ,  Paul Loewenstein ,  Louis F. Coffin, III

发明人： Zahir Ebrahim ,  Satyanarayana Nishtala ,  William C. Van Loo ,  Kevin Normoyle ,  Paul Loewenstein ,  Louis F. Coffin, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0822

摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.

摘要翻译： 多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。 一些子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器以及相应的主缓存标签集（Etag），包括由高速缓冲存储器存储的每个数据块的一个Etag。 每个数据处理器包括一个接口，用于向系统控制器发送存储器事务请求，并接收来自系统控制器的高速缓存事务请求，对应于其他数据处理器的存储器事务请求。 系统控制器包括事务激活逻辑，用于当其满足预定义的激活准则时激活每个所述存储器事务请求，并且用于阻止每个所述存储器事务请求直到满足预定义的激活标准。 活动事务状态表存储表示已激活的存储器事务请求的状态数据，包括每个激活的事务的地址值。 事务激活逻辑包括比较器逻辑，用于将每个存储器事务请求与所有激活的存储器事务请求的活动事务状态数据进行比较，以便检测特定存储器事务请求的激活是否违反预定义的激活标准。 对于回写事务有一些例外，用于访问映射到相同高速缓存行的未决事务，先前激活的事务的数据块的传入事务将被阻止，直到映射到同一高速缓存行的挂起事务完成。

公开(公告)号：US5862356A

公开(公告)日：1999-01-19

申请号：US870438

申请日：1997-06-04

申请人： Kevin B. Normoyle ,  Zahir Ebrahim ,  Satyanarayana Nishtala ,  William C. Van Loo ,  Louis F. Coffin, III

发明人： Kevin B. Normoyle ,  Zahir Ebrahim ,  Satyanarayana Nishtala ,  William C. Van Loo ,  Louis F. Coffin, III

IPC分类号： G06F15/16 ,  G06F13/368 ,  G06F13/374 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F13/368 ,  G06F13/374

摘要： The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitration latency for retaining the current bus master is one system clock cycle while the latency for selecting and switching bus masters is two system clock cycles. In this implementation, a last port driver is the only sub-system permitted to assert a bus request in a clock cycle and immediately drive the system bus in the next immediate clock cycle. Conversely, when a second sub-system which is not the last port driver needs to drive an inactive system bus, the second sub-system asserts its bus request line in a first clock cycle, and arbitration occurs within all the respective bus arbiters occurs in a second clock cycle.

摘要翻译： 本发明提供了一种可扩展的，模块化和流水线分布式总线仲裁系统，用于有效地分辨耦合到公共系统总线的子系统（例如处理器）之间的总线争用。 仲裁系统包括多个分布式总线仲裁器，其接收来自子系统的总线请求并独立地确定下一个总线主机。 仲裁协议使仲裁过程能够从临界定时路径中消除，从而允许系统以给定的集成电路（IC）技术可能的最大系统时钟频率工作，以减少整体系统时钟延迟。 在仲裁时钟周期期间，子系统之间的任何改变都是基于任何在仲裁时钟周期之前的时钟周期期间有效的系统总线请求，并且独立于在系统总线请求期间断言的任何系统总线请求 仲裁时钟周期。 此外，仲裁协议优先处理当前总线主机，即总线主机驱动系统总线。 无论处理器速度如何，每个仲裁任务都在系统时钟周期内完成。 因此，用于保留当前总线主机的仲裁延迟是一个系统时钟周期，而用于选择和切换总线主机的延迟是两个系统时钟周期。 在此实现中，最后一个端口驱动程序是允许在时钟周期内断言总线请求的唯一子系统，并在下一个即时时钟周期内立即驱动系统总线。 相反，当不是最后端口驱动器的第二子系统需要驱动非活动系统总线时，第二子系统在第一时钟周期内断言其总线请求线，并且在所有相应的总线仲裁器内进行仲裁发生在 第二个时钟周期。

公开(公告)号：US5346194A

公开(公告)日：1994-09-13

申请号：US88180

申请日：1993-07-07

申请人： Louis F. Coffin, III

发明人： Louis F. Coffin, III

IPC分类号： B25B5/06 ,  B25B5/08 ,  B25B5/12 ,  B25B1/14

CPC分类号： B25B5/08 ,  B25B5/06 ,  B25B5/068 ,  B25B5/12 ,  B25B5/127

摘要： An improved carpenter's clamp is provided for easily securing a workpiece. The clamp has a C-shaped frame that can be mounted to a holding surface. The frame has a top and a bottom receiver aperture. A slide bar is slidably mounted in an axial direction within the top and bottom receiver apertures, and a handle is pivotally attached to the frame to provide a downward axial force to the slide bar when the handle is lowered. A toggle link is provided allowing the handle to be locked in a downward position thereby locking said slide bar in a secured position. A holding arm having a holding tip at a distal end is slidably mounted to the slide bar, and the slide bar is positioned between a pair of bias pins on the holding arm so that a workpiece can be held between the holding surface and the holding tip when a downward force is applied to the handle.

摘要翻译： 提供了一种改进的木匠夹具，用于容易地固定工件。 夹具具有可以安装到保持表面的C形框架。 该框架具有顶部和底部接收器孔径。 滑动杆在轴向方向可滑动地安装在顶部和底部接收器孔内，并且手柄枢转地附接到框架，以在手柄下降时向滑动杆提供向下的轴向力。 提供了一种切换连杆，允许把手被锁定在向下的位置，从而将所述滑动杆锁定在固定位置。 具有在前端的保持尖端的保持臂可滑动地安装在滑动杆上，并且滑动杆位于保持臂上的一对偏置销之间，使得工件能够保持在保持表面和保持尖端之间 当向手柄施加向下的力时。

公开(公告)号：US07783247B2

公开(公告)日：2010-08-24

申请号：US11275855

申请日：2006-01-31

申请人： Louis F. Coffin, III

发明人： Louis F. Coffin, III

IPC分类号： H04H20/74

CPC分类号： H04H40/90 ,  H04N7/20

摘要： A home satellite receiving system employs a transmodulating outdoor unit (ODU) that tunes to multiple signals, demodulates those signals into streams of data packets, and filters the streams of data packets to select data packets pertaining to viewer-specified programs. The ODU then constructs an integrated bitstream from the selected data packets and modulates that bitstream for transmission to an indoor IRD. This allows transfer of multiple programs from different satellite sources to the indoor IRD over a single coaxial cable. The indoor IRD reconstructs the packet stream timing for the viewer-specified programs from the integrated bitstream.

摘要翻译： 家庭卫星接收系统采用调谐到多个信号的变换室外单元（ODU），将这些信号解调成数据分组流，并对数据分组流进行过滤以选择与观众指定的节目有关的数据分组。 然后，ODU从所选择的数据分组中构建一个集成的比特流，并调制该比特流以传输到室内IRD。 这允许通过单根同轴电缆将多个程序从不同的卫星源传输到室内IRD。 室内IRD从集成比特流重建用于观众指定节目的分组流定时。

公开(公告)号：US07281186B2

公开(公告)日：2007-10-09

申请号：US11121583

申请日：2005-05-04

申请人： Louis F. Coffin, III ,  Deepak Prakash ,  James A. Lundblad

发明人： Louis F. Coffin, III ,  Deepak Prakash ,  James A. Lundblad

IPC分类号： G06F11/00

CPC分类号： H04N21/434

摘要： A method and apparatus for managing error/status information generated in the demultiplexing, processing, and handling of data packets from a video transport stream. Error/status information is organized into control fields of error/status packets. The error/status packets are sent to dedicated error/status buffers of bulk system memory where they can be accessed by a system processor during the reconfiguration and decoding of video programming.

摘要翻译： 一种用于管理从视频传输流解复用，处理和处理数据分组中产生的错误/状态信息的方法和装置。 错误/状态信息被组织成错误/状态包的控制字段。 错误/状态数据包被发送到大容量系统存储器的专用错误/状态缓冲器，在视频编程的重新配置和解码期间，它们可被系统处理器访问。

公开(公告)号：US07010265B2

公开(公告)日：2006-03-07

申请号：US10154615

申请日：2002-05-22

申请人： Louis F. Coffin, III

发明人： Louis F. Coffin, III

IPC分类号： H04H1/00

CPC分类号： H04H40/90 ,  H04N7/20

摘要： A home satellite receiving system employs a transmodulating outdoor unit (ODU) that tunes to multiple signals, demodulates those signals into streams of data packets, and filters the streams of data packets to select data packets pertaining to viewer-specified programs. The ODU then constructs an integrated bitstream from the selected data packets and modulates that bitstream for transmission to an indoor IRD. This allows transfer of multiple programs from different satellite sources to the indoor IRD over a single coaxial cable. The indoor IRD reconstructs the packet stream timing for the viewer-specified programs from the integrated bitstream.

公开(公告)号：US06983408B2

公开(公告)日：2006-01-03

申请号：US10093646

申请日：2002-03-08

申请人： Louis F. Coffin, III ,  Deepak Prakash ,  James A. Lundblad

发明人： Louis F. Coffin, III ,  Deepak Prakash ,  James A. Lundblad

IPC分类号： G06F11/273

CPC分类号： H04N21/434

摘要： A method and apparatus for managing error/status information generated in the demultiplexing, processing, and handling of data packets from a video transport stream. Error/status information is organized into control fields of error/status packets. The error/status packets are sent to dedicated error/status buffers of bulk system memory where they can be accessed by a system processor during the reconfiguration and decoding of video programming.

摘要翻译： 一种用于管理从视频传输流解复用，处理和处理数据分组中产生的错误/状态信息的方法和装置。 错误/状态信息被组织成错误/状态包的控制字段。 错误/状态数据包被发送到大容量系统存储器的专用错误/状态缓冲器，在视频编程的重新配置和解码期间，它们可被系统处理器访问。

公开(公告)号：US06956622B2

公开(公告)日：2005-10-18

申请号：US10185951

申请日：2002-06-27

申请人： Louis F. Coffin, III

发明人： Louis F. Coffin, III

IPC分类号： H04N11/24 ,  H04N5/40 ,  H04N5/44 ,  H04N5/455 ,  H04N9/64 ,  H04N9/66 ,  H04N9/77

CPC分类号： H04N11/004

摘要： A luminance component of a video signal is modulated in a first frequency band. A chrominance component of the video signal is modulated in a second frequency band. The modulated luminance component and the modulated chrominance component are then transmitted across a communication link.

摘要翻译： 在第一频带中调制视频信号的亮度分量。 视频信号的色度分量在第二频带中被调制。 经调制的亮度分量和调制的色度分量然后通过通信链路传输。