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公开(公告)号：US20130160114A1
公开(公告)日：2013-06-20
申请号：US13329583
申请日：2011-12-19
IPC分类号： G06F21/22
CPC分类号： G06F21/606 , G06F21/6218
摘要： A circuit arrangement and method utilize a process context translation data structure in connection with an on-chip network of a processor chip to implement secure inter-thread communication between hardware threads in the processor chip. The process context translation data structure maps processes to inter-thread communication hardware resources, e.g., the inbox and/or outbox buffers of a NOC processor, such that a user process is only allowed to access the inter-thread communication hardware resources that it has been granted access to, and typically with only certain types of authorized access types. Moreover, a hypervisor or supervisor may manage the process context translation data structure to grant or deny access rights to user processes such that, once those rights are established in the data structure, user processes are permitted to perform inter-thread communications without requiring context switches to a hypervisor or supervisor in order to handle the communications.
摘要翻译： 电路布置和方法利用与处理器芯片的片上网络相关联的处理上下文转换数据结构来实现处理器芯片中的硬件线程之间的安全的线程间通信。 进程上下文转换数据结构将进程映射到线程间通信硬件资源，例如NOC处理器的收件箱和/或发件箱缓冲器，使得用户进程仅被允许访问它所具有的线程间通信硬件资源 被授权访问，并且通常仅具有某些类型的授权访问类型。 此外，管理程序或管理程序可以管理进程上下文转换数据结构以授予或拒绝对用户进程的访问权限，使得一旦在数据结构中建立这些权限，允许用户进程执行线程间通信，而不需要上下文切换 到管理程序或主管以处理通信。
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2.发明申请REGULAR EXPRESSION SEARCHES UTILIZING GENERAL PURPOSE PROCESSORS ON A NETWORK INTERCONNECT 失效在网络互连中使用一般用途处理器的常规表达式搜索公开(公告)号：US20120221711A1
公开(公告)日：2012-08-30
申请号：US13036779
申请日：2011-02-28
IPC分类号： G06F15/16
CPC分类号： H04L67/28
摘要： A first hardware node in a network interconnect receives a data packet from a network. The first hardware node examines the data packet for a regular expression. In response to the first hardware node failing to identify the regular expression in the data packet, the data packet is forwarded to a second hardware node in the network interconnect for further examination of the data packet in order to search for the regular expression in the data packet.
摘要翻译： 网络互连中的第一个硬件节点从网络接收数据包。 第一个硬件节点检查正则表达式的数据包。 响应于第一硬件节点未能识别数据分组中的正则表达式，数据分组被转发到网络互连中的第二硬件节点，以进一步检查数据分组，以便搜索数据中的正则表达式 包。
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3.发明授权Branch prediction technique using instruction for resetting result table pointer 有权分支预测技术，使用指令重置结果表指针公开(公告)号：US08078850B2
公开(公告)日：2011-12-13
申请号：US12108846
申请日：2008-04-24
CPC分类号： G06F9/3844 , G06F9/30145 , G06F9/322 , G06F9/3806
摘要： Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results.
摘要翻译： 公开了一种用于在计算机处理器中进行分支预测的方法，装置和产品，包括：在分支出现多于一次的算法中记录分支出现次序，每个分支的结果包括保持指针 到最近记录的结果的位置; 完成算法后，将指针复位到第一记录结果的位置; 并根据记录的结果预测分支的随后的分支结果。
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4.发明授权Regular expression searches utilizing general purpose processors on a network interconnect 失效正则表达式在网络互连上搜索利用通用处理器公开(公告)号：US08719404B2
公开(公告)日：2014-05-06
申请号：US13036779
申请日：2011-02-28
IPC分类号： G06F15/177
CPC分类号： H04L67/28
摘要： A first hardware node in a network interconnect receives a data packet from a network. The first hardware node examines the data packet for a regular expression. In response to the first hardware node failing to identify the regular expression in the data packet, the data packet is forwarded to a second hardware node in the network interconnect for further examination of the data packet in order to search for the regular expression in the data packet.
摘要翻译： 网络互连中的第一个硬件节点从网络接收数据包。 第一个硬件节点检查正则表达式的数据包。 响应于第一硬件节点未能识别数据分组中的正则表达式，数据分组被转发到网络互连中的第二硬件节点，以进一步检查数据分组，以便搜索数据中的正则表达式 包。
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公开(公告)号：US08560897B2
公开(公告)日：2013-10-15
申请号：US12961947
申请日：2010-12-07
IPC分类号： G06F11/00
CPC分类号： G06F11/0727 , G06F11/0724 , G06F11/073 , G06F11/0772
摘要： A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice.
摘要翻译： 公开了一种用于管理采用锁定的存储器系统中的硬故障的技术。 内存系统中的内存单元维护错误计数。 当错误计数表示硬故障时，内存单元被锁定以供进一步使用。 分配一组任意错误计数器来记录访问内存单元所产生的错误。 本发明的实施例有利地使得即使在一个或多个内部硬盘存储器故障之后，系统也能够继续可靠的操作。 其他实施例有利地使得制造商能够回收部分故障的设备，并且将设备部署为具有较低性能规范而不是丢弃设备，否则将由常规实践指出。
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公开(公告)号：US20130160026A1
公开(公告)日：2013-06-20
申请号：US13330850
申请日：2011-12-20
CPC分类号： G06F9/546
摘要： A circuit arrangement, method, and program product for communicating data between hardware threads of a network on a chip processing unit utilizes shared inboxes to communicate data to pools of hardware threads. The associated hardware in the pools threads receive data packets from the shared inboxes in response to issuing work requests to an associated shared inbox. Data packets include a source identifier corresponding to a hardware thread from which the data packet was generated, and the shared inboxes may manage data packet distribution to associated hardware threads based on the source identifier of each data packet. A shared inbox may also manage workload distribution and uneven workload lengths by communicating data packets to hardware threads associated with the shared inbox in response to receiving work requests from associated hardware threads.
摘要翻译： 用于在芯片处理单元上的网络的硬件线程之间传送数据的电路装置，方法和程序产品利用共享的收件箱将数据传送到硬件线程池。 响应于向相关联的共享收件箱发出工作请求，池线程中的关联硬件从共享收件箱接收数据包。 数据分组包括对应于生成数据分组的硬件线程的源标识符，并且共享收件箱可以基于每个数据分组的源标识来管理相关联的硬件线程的数据分组分发。 通过将数据包传送到与共享收件箱相关联的硬件线程，响应于从相关联的硬件线程接收工作请求，共享收件箱还可以管理工作负载分布和不均衡的工作负载长度。
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公开(公告)号：US08990833B2
公开(公告)日：2015-03-24
申请号：US13330850
申请日：2011-12-20
CPC分类号： G06F9/546
摘要： A circuit arrangement, method, and program product for communicating data between hardware threads of a network on a chip processing unit utilizes shared inboxes to communicate data to pools of hardware threads. The associated hardware in the pools threads receive data packets from the shared inboxes in response to issuing work requests to an associated shared inbox. Data packets include a source identifier corresponding to a hardware thread from which the data packet was generated, and the shared inboxes may manage data packet distribution to associated hardware threads based on the source identifier of each data packet. A shared inbox may also manage workload distribution and uneven workload lengths by communicating data packets to hardware threads associated with the shared inbox in response to receiving work requests from associated hardware threads.
摘要翻译： 用于在芯片处理单元上的网络的硬件线程之间传送数据的电路装置，方法和程序产品利用共享的收件箱将数据传送到硬件线程池。 响应于向相关联的共享收件箱发出工作请求，池线程中的关联硬件从共享收件箱接收数据包。 数据分组包括对应于生成数据分组的硬件线程的源标识符，并且共享收件箱可以基于每个数据分组的源标识来管理相关联的硬件线程的数据分组分发。 通过将数据包传送到与共享收件箱相关联的硬件线程，响应于从相关联的硬件线程接收工作请求，共享收件箱还可以管理工作负载分布和不均衡的工作负载长度。
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公开(公告)号：US08640230B2
公开(公告)日：2014-01-28
申请号：US13329583
申请日：2011-12-19
IPC分类号： G06F12/00
CPC分类号： G06F21/606 , G06F21/6218
摘要： A circuit arrangement and method utilize a process context translation data structure in connection with an on-chip network of a processor chip to implement secure inter-thread communication between hardware threads in the processor chip. The process context translation data structure maps processes to inter-thread communication hardware resources, e.g., the inbox and/or outbox buffers of a NOC processor, such that a user process is only allowed to access the inter-thread communication hardware resources that it has been granted access to, and typically with only certain types of authorized access types. Moreover, a hypervisor or supervisor may manage the process context translation data structure to grant or deny access rights to user processes such that, once those rights are established in the data structure, user processes are permitted to perform inter-thread communications without requiring context switches to a hypervisor or supervisor in order to handle the communications.
摘要翻译： 电路布置和方法利用与处理器芯片的片上网络相关联的处理上下文转换数据结构来实现处理器芯片中的硬件线程之间的安全的线程间通信。 进程上下文转换数据结构将进程映射到线程间通信硬件资源，例如NOC处理器的收件箱和/或发件箱缓冲器，使得用户进程仅被允许访问它所具有的线程间通信硬件资源 被授权访问，并且通常仅具有某些类型的授权访问类型。 此外，管理程序或管理程序可以管理进程上下文转换数据结构以授予或拒绝对用户进程的访问权限，使得一旦在数据结构中建立这些权限，允许用户进程执行线程间通信，而不需要上下文切换 到管理程序或主管以处理通信。
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9.发明申请PROVIDING PERFORMANCE TUNED VERSIONS OF COMPILED CODE TO A CPU IN A SYSTEM OF HETEROGENEOUS CORES 有权将编译代码的性能调整版本提供给异构系统中的CPU公开(公告)号：US20130185705A1
公开(公告)日：2013-07-18
申请号：US13352721
申请日：2012-01-18
CPC分类号： G06F8/443 , G06F8/47 , G06F8/54 , G06F9/44521 , G06F9/44542 , G06F9/5027
摘要： A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if a compute node has three different types of processors with three different architecture implementations, the compiler may compile the source code and generate three versions of object code where each version is optimized for one of the three different processor types. After compiling the source code, the resultant executable code may contain the necessary information for selecting between the three versions. For example, when a program loader assigns the executable code to the processor, the system determines the processor's type and ensures only the optimized version that corresponds to that type is executed. Thus, the operating system is free to assign the executable code to any of the different types of processors.
摘要翻译： 编译器可以优化源代码和任何引用的库以在多个不同的处理器架构实现上执行。 例如，如果计算节点具有三种不同类型的具有三种不同架构实现的处理器，则编译器可以编译源代码并生成三种版本的目标代码，其中每个版本针对三种不同处理器类型之一进行了优化。 在编译源代码之后，生成的可执行代码可能包含用于在三个版本之间进行选择的必要信息。 例如，当程序加载器将可执行代码分配给处理器时，系统确定处理器的类型并确保仅执行与该类型对应的优化版本。 因此，操作系统可以自由地将可执行代码分配给任何不同类型的处理器。
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公开(公告)号：US09176885B2
公开(公告)日：2015-11-03
申请号：US13355613
申请日：2012-01-23
CPC分类号： G06F12/0888 , G06F13/28
摘要： A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.
摘要翻译： 电路装置和方法利用高速缓存注入逻辑来执行高速缓存注入和锁定操作，以将高速缓存行注入到高速缓冲存储器中，并且将高速缓存行与高速缓存行的通信并行地主动地锁定在高速缓存存储器中。 高速缓存注入逻辑可以另外限制可以存储在高速缓冲存储器中的锁定高速缓存行的最大数量，例如通过中止高速缓存注入和锁定操作，在不锁定的情况下注入高速缓存行，或者解锁和/或驱逐另一个高速缓存行 在缓存中。
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