摘要:
A step-up converter includes an inductor which receives input voltage Vi at one end, a first FET of the first conduction type which functions as a switch for determining whether or not energy is accumulated in the inductor, a second FET of the second conduction type which rectifies a current output from the other end of the inductor, an output capacitor having an end connected to the source of the second FET, a current detection circuit, and a feedback control circuit. The current detection circuit detects a current flowing through the first N-channel FET to output current detection signal Vc. The feedback control circuit controls the operations of the first N-channel FET and a P-channel FET based on current detection signal Vc.
摘要:
The present invention provides a current-mode control step-up converter capable of reducing the minimum duty ratio to a sufficiently small value and facilitating the setting of the maximum duty ratio. The step-up converter comprises a current detector 9 for generating a current detection signal Vc corresponding to the current of a rectifier 4; an error amplifier 8 for generating an error signal Ve corresponding to an output DC voltage Vo; and a control circuit 10 for turning ON/OFF the main switch 3 on the basis of the current detection signal Vc and the error signal Ve. The control circuit 10 comprises a comparator 11 and a timer circuit 12. With this configuration, the ON time of the main switch 3 is set at a predetermined value, and the valley value of an inductor current changing in a triangular waveform is controlled. Hence, the OFF time of the main switch is adjusted to stabilize the output. Since the ON time of the main switch 3 can be set as desired, the minimum duty ratio can be reduced to zero or a sufficiently small value.
摘要:
In a DC-DC converter conforming to the current mode control system, in which the valley value of an inductor current is controlled for output control, a current detection circuit 6 is configured to detect the current flowing from a low-side FET 2 to an inductor 3 using an FET 60, an NPN transistor 61, an NPN transistor 62, a PNP transistor 64, a PNP transistor 65 and a resistor 66, to detect the current flowing from the inductor 3 to the low-side FET 2 using an FET 67, a differential amplifier 68, an FET 69 and the resistor 66, and to output a current detection signal Vc.
摘要:
The present invention is intended to provide a DC-DC converter, in which the relationship between the duty ratio of a drive signal and the output DC voltage is nonlinear, being characterized in that the relationship between an error signal and the output DC voltage is linear, and that the design of stabilizing the feedback system is facilitated. The DC-DC converter comprises an error-amplifier circuit for generating the error signal that is obtained by amplifying the error between the output and a target value, an oscillating circuit for generating a triangular wave signal having an amplitude corresponding to the error signal, and a comparison circuit for comparing the triangular wave signal with a reference signal having a predetermined value and for generating the drive signal to turn ON/OFF a switching device.
摘要:
A step-up converter includes an inductor which receives input voltage Vi at one end, a first FET of the first conduction type which functions as a switch for determining whether or not energy is accumulated in the inductor, a second FET of the second conduction type which rectifies a current output from the other end of the inductor, an output capacitor having an end connected to the source of the second FET, a current detection circuit, and a feedback control circuit. The current detection circuit detects a current flowing through the first N-channel FET to output current detection signal Vc. The feedback control circuit controls the operations of the first N-channel FET and a P-channel FET based on current detection signal Vc.
摘要:
An output detection feedback section (5) for controlling the power supply output voltage of a converter unit (4) in response to an error signal Ve has an error amplifier (26) for outputting the error signal Ve, a phase compensation circuit (41), a state detection circuit (42), and a response compensation circuit (43) for setting the voltage of a capacitor (29) of the phase compensation circuit (41) to a predetermined value. When output voltage is switched, the output voltage is fixed at the predetermined value in a DC manner while a transitional response of the error signal (Ve) is accelerated, so that the output voltage is changed at a high speed to a desired value and the overshoot and undershoot are suppressed around the desired value.
摘要:
A DC-DC converter has switching means which generates a continuous switching voltage having a specified period from an input voltage and outputs the generated switching voltage, output voltage generating means which receives the switching voltage at an inductor and generates an output voltage obtained by rectifying and smoothing a voltage generated in the inductor, lamp signal generating means which generates a lamp signal and outputs the generated lamp signal, and control means which performs an arithmetic operation using a current signal relative to a current flowing in the inductor, an error signal relative to the output voltage, and the lamp signal to generate a control signal for controlling the operation of the switching means and outputs the generated control signal to the switching means. The lamp signal generating means includes first signal generating means for generating a first output signal based on a frequency divided signal having first and second periods obtained by dividing the time of a clock signal having the specified period and second signal generating means for generating a second output signal having a phase 180 degrees different from the phase of the first output signal based on the frequency divided signal, generates the lamp signal which rises after being held at a constant value for a specified time period in each of the first and second periods, and outputs the generated lamp signal.
摘要:
An LED is provided with a p-type semiconductor region in the shape of an island being buried in an n-type semiconductor region from the surface of it, and forms a pn junction at the interface between these n-type region and p-type region. The pn junction has a bottom junction at the bottom of the n-type region and a side junction at the peripheral side face. The bottom junction comprises a first subjunction being deep and constant in junction depth and a second subjunction varying continuously in junction depth. The depth of the second subjunction is shallower than the depth of the first subjunction. The p-type region portion above the second subjunction is thinner in thickness than the p-type region portion above the first subjunction. A light passing through the p-type region portion of the former is less in absorption and more in optical power of the output light. The total power of the output light of the whole LED is increased correspondingly to reduction in thickness of the p-type region.
摘要:
A substrate polishing apparatus is provided with: a turntable (36) having a polishing surface; a plate (11) having an attaching surface to which GaAs semiconductor wafers (12a through 12d) are attached; points (42a through 42d) for adjusting the gap between the GaAs semiconductor wafers (12a through 12d) attached to the plate (11) and the polishing surface of the turntable (36); and notches (16a through 16d) formed so that they extend from the portions of the plate (11), where the points (42a through 42d) are formed, to the circumference of the plate (11). A method for polishing a semiconductor substrate employs the substrate polishing apparatus.
摘要:
In a fabricating method for an end face light emitting type LED array, p-type regions are formed by diffusing impurities into portions of a semiconductor substrate, using a diffusion prevention film as a mask. Subsequently, using the diffusion prevention film as a mask again, the semiconductor substrate is etched to form a concave portion therein so that light-emission end faces are formed on a side of the concave portion. With this arrangement, a positional misalignment between the p-type regions and the light-emission end faces is prevented.