公开(公告)号：US07529962B1

公开(公告)日：2009-05-05

申请号：US12098038

申请日：2008-04-04

申请人： Malede Wondmagegne Berhanu ,  Christopher Douglas Hanudel ,  Mark William Kuemerle ,  David Wills Milton ,  Clarence Rosser Ogilvie ,  Jack Robert Smith

发明人： Malede Wondmagegne Berhanu ,  Christopher Douglas Hanudel ,  Mark William Kuemerle ,  David Wills Milton ,  Clarence Rosser Ogilvie ,  Jack Robert Smith

IPC分类号： G06F1/04 ,  H04L7/00

CPC分类号： H04L7/0338 ,  H04L7/0008

摘要： In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.

摘要翻译： 在一个一般实施例中，提供了一种设计结构，其包括具有至少一个缓冲器的第一延迟线，第一延迟线用于移位时钟，第二延迟线具有至少一个缓冲器，第二延迟线用于移位数据， 以及适于识别数据窗口的预定部分的逻辑块。 此外，逻辑块监视沿延迟线的预定部分的时钟信号，以识别数据窗口的预定部分。 一旦识别了数据窗口的预定部分，逻辑块将与预定部分相关联的数据转发到输出引脚，条件是不存在存储元件，并且条件是不存在反馈线。