公开(公告)号：US07529962B1

公开(公告)日：2009-05-05

申请号：US12098038

申请日：2008-04-04

申请人： Malede Wondmagegne Berhanu ,  Christopher Douglas Hanudel ,  Mark William Kuemerle ,  David Wills Milton ,  Clarence Rosser Ogilvie ,  Jack Robert Smith

发明人： Malede Wondmagegne Berhanu ,  Christopher Douglas Hanudel ,  Mark William Kuemerle ,  David Wills Milton ,  Clarence Rosser Ogilvie ,  Jack Robert Smith

IPC分类号： G06F1/04 ,  H04L7/00

CPC分类号： H04L7/0338 ,  H04L7/0008

摘要： In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.

摘要翻译： 在一个一般实施例中，提供了一种设计结构，其包括具有至少一个缓冲器的第一延迟线，第一延迟线用于移位时钟，第二延迟线具有至少一个缓冲器，第二延迟线用于移位数据， 以及适于识别数据窗口的预定部分的逻辑块。 此外，逻辑块监视沿延迟线的预定部分的时钟信号，以识别数据窗口的预定部分。 一旦识别了数据窗口的预定部分，逻辑块将与预定部分相关联的数据转发到输出引脚，条件是不存在存储元件，并且条件是不存在反馈线。

公开(公告)号：US06820254B2

公开(公告)日：2004-11-16

申请号：US09681327

申请日：2001-03-19

申请人： Jack Robert Smith ,  Sebastian Theodore Ventrone

发明人： Jack Robert Smith ,  Sebastian Theodore Ventrone

IPC分类号： G06F945

CPC分类号： G06F8/443

摘要： A data processing system includes a central processing unit (CPU) in communication with a system memory. Within the system memory, there is stored legacy code that does not utilize the full features of the CPU. The data processing system also includes a code-optimizing coprocessor in communication with the CPU and the system memory. Control logic within the code-optimizing coprocessor causes the code-optimizing coprocessor to generate optimized code from the legacy code at the same time the CPU executes the legacy code, such that the optimized code is tailored according to the CPU. After the code-optimizing coprocessor has generated at least some optimized code, the code-optimizing coprocessor causes the CPU to automatically utilize at least some optimized code in lieu of at least some of the legacy code.

摘要翻译： 数据处理系统包括与系统存储器通信的中央处理单元（CPU）。 在系统内存中，存储了不利用CPU全部功能的旧版代码。 数据处理系统还包括与CPU和系统存储器通信的代码优化协处理器。 代码优化协处理器内的控制逻辑使得代码优化协处理器在CPU执行遗留代码的同时从旧代码生成优化的代码，使得优化的代码根据CPU进行调整。 在代码优化协处理器已经生成了至少一些优化的代码之后，代码优化协处理器使CPU自动利用至少一些优化的代码来代替至少一些遗留代码。

公开(公告)号：US07080344B2

公开(公告)日：2006-07-18

申请号：US10604071

申请日：2003-06-25

申请人： Stanislav Peter Bajuk ,  Jack Robert Smith ,  Sebastian Theodore Ventrone

发明人： Stanislav Peter Bajuk ,  Jack Robert Smith ,  Sebastian Theodore Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068

摘要： A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect's type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

摘要翻译： 一种存储和修改寄存器传输语言（RTL）的方法和系统，描述逻辑类型。 在声明信号互连时，基于信号互连的类型，为信号互连定义了寄存器传输语言的语言扩展。 语言扩展允许不同的信号互连类型，例如与现场可编程门阵列（FPGA）和标准单元一起使用的信号互连类型存储在相同的文件阵列层次结构中。 这种存储有助于改变逻辑类型，从而最终导致集成电路（IC）更小（使用更多标准单元）或更灵活（使用更多的FPGA单元）。 在物理设计周期内执行从一个RTL类型到另一个RTL类型的转换，其中在掩蔽最终芯片设计之前执行组件（信息）的布线，定时和布局。

公开(公告)号：US06834353B2

公开(公告)日：2004-12-21

申请号：US09682816

申请日：2001-10-22

申请人： Jack Robert Smith ,  Sebastian Theodore Ventrone

发明人： Jack Robert Smith ,  Sebastian Theodore Ventrone

IPC分类号： G06F132

CPC分类号： G06F1/3203

摘要： In a first aspect, a method is provided for conserving power in a processing integrated circuit. The method includes the steps of (1) calculating power consumption for executing an instruction and data corresponding to the instruction; and (2) executing the instruction if such execution does not exceed a predetermined power level. In a second aspect, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of (1) comparing a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and (2) if the total power exceeds the power budget, freezing execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution was frozen. Numerous other aspects are provided, as are systems and apparatus.

摘要翻译： 在第一方面，提供了一种用于在处理集成电路中节省功率的方法。 该方法包括以下步骤：（1）计算用于执行指令的功耗和对应于该指令的数据; 和（2）如果这样的执行不超过预定功率电平，则执行指令。 在第二方面，提供一种用于在采用多个执行单元的处理集成电路中节省功率的方法。 该方法包括以下步骤：（1）将由处理集成电路消耗的总功率与处理集成电路的功率预算进行比较; 以及（2）如果总功率超过功率预算，则冻结多个执行单元之一的指令的执行，以便允许执行指令在执行被冻结的较后时间继续。 还提供了许多其他方面，系统和装置也是如此。