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    Scalable codebook correlation for cloud scale topology
    1.
    发明授权
    Scalable codebook correlation for cloud scale topology 有权
    云规模拓扑的可扩展码本相关性

    公开(公告)号：US08832498B1

    公开(公告)日：2014-09-09

    申请号：US13561340

    申请日：2012-07-30

    Applicant: Manoj Kumar Jain ,  Siju Viswanath Koodali Edathil ,  Kottolli Vishweshwara Arun

    Inventor： Manoj Kumar Jain ,  Siju Viswanath Koodali Edathil ,  Kottolli Vishweshwara Arun

    IPC: G06F11/00 ,  G06F17/30

    CPC classification number: G06F17/30017 ,  G06F11/0709 ,  G06F11/079 ,  G06F11/3034 ,  G06F11/327 ,  G06F11/3409 ,  G06F11/3442 ,  G06F11/3485 ,  G06F17/30144 ,  G06F2201/86 ,  H04L41/0631

    Abstract: A system and algorithm to map alerts to a problem domain is provided so that the size of a codebook for the problem domain may be reduced and correlated independently of the general system and/or other problem domains in the system topology. When one or more symptoms of a fault appear in the system topology, the problem domain is discovered dynamically and the codebook for the problem domain generated dynamically. The system described herein provides for computation of a problem domain that has a reduced object repository for a set of objects which are directly or indirectly impacted by monitored symptoms. Multiple problem domains may be independently computed in order to build one or more codebooks. Each problem domain may be smaller compared to a system topology resulting in scale and performance improvements for codebook computation and correlation.

    Abstract translation: 提供了一种将警报映射到问题域的系统和算法，使得问题域的码本的大小可以与系统拓扑中的通用系统和/或其他问题域无关地减小和相关。 当系统拓扑中出现一个或多个故障症状时，动态发现问题域，动态生成问题域的码本。 本文描述的系统提供了对于直接或间接地受监视症状影响的一组对象具有减少的对象库的问题域的计算。 可以独立地计算多个问题域以构建一个或多个码本。 与系统拓扑相比，每个问题域可能会较小，从而导致码本计算和相关性的规模和性能改进。

    Selecting a path through a network
    2.
    发明授权
    Selecting a path through a network 有权
    选择通过网络的路径

    公开(公告)号：US08259736B2

    公开(公告)日：2012-09-04

    申请号：US12638794

    申请日：2009-12-15

    Applicant: Manoj Kumar Jain

    Inventor： Manoj Kumar Jain

    IPC: H04L12/28 ,  H04L12/56

    CPC classification number: H04L45/00 ,  H04L45/30 ,  H04L47/724 ,  H04L47/762

    Abstract: In a method for selecting a path through a network of nodes from a source device to a destination device, per hop behaviors (PHB) of the nodes is identified and a path entropy for a plurality of candidate paths through the network between the source device and the destination device are derived based upon the PHBs of the nodes. In addition, one of the plurality of candidate paths is selected to communicate data from the source device to the destination device based on the path entropies of the plurality of candidate paths.

    Abstract translation: 在从源设备到目的设备的选择通过节点网络的路径的方法中，识别节点的每跳行为（PHB），以及通过网络在源设备和 基于节点的PHB导出目的地设备。 此外，多个候选路径中的一个被选择为基于多个候选路径的路径熵将源从设备传送到目的地设备。

    Conductor reticulation for improved device planarity
    10.
    发明授权
    Conductor reticulation for improved device planarity 失效
    导体网状结构提高了器件平面度

    公开(公告)号：US06495907B1

    公开(公告)日：2002-12-17

    申请号：US08473404

    申请日：1995-06-07

    Applicant: Manoj Kumar Jain ,  Michael Francis Chisholm

    Inventor： Manoj Kumar Jain ,  Michael Francis Chisholm

    IPC: H01L23495

    CPC classification number: H01L23/528 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.

    Abstract translation: 公开了一种半导体器件及其制造方法，其使用网状导体和宽度选择性平坦化层间电介质（ILD）沉积工艺来改善互连层的平面度。 使用网状导体52代替固体导体，其中所需的固体导体宽度将大于工艺和设计依赖的临界宽度（小于临界宽度的导体可以通过适当的ILD沉积而平坦化）。 网状导体优选地由具有小于临界宽度的整体形成的导电段形成，使得通过诸如高密度等离子体氧化物沉积（通过在氧 - 氩气氛中的硅烷分解形成的工艺中形成的）形成的ILD 32， 反溅射偏压）或旋转涂层将较大的网状导体平坦化，因为其将小于临界宽度的固体导体。 使用这种技术，可以完全减少或避免后续的ILD平坦化步骤，例如化学机械抛光或回蚀。

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