公开(公告)号：US20080021771A1

公开(公告)日：2008-01-24

申请号：US11755567

申请日：2007-05-30

Applicant: Ling Wu ,  David McCurley ,  Bin Zhou ,  Mark Chan ,  Ramesh Anantharamaiah

Inventor： Ling Wu ,  David McCurley ,  Bin Zhou ,  Mark Chan ,  Ramesh Anantharamaiah

IPC: G06Q30/00 ,  G06F17/30

CPC classification number: G06Q30/00 ,  G06Q30/0222 ,  G06Q30/0239

Abstract: A computer-implemented method of determining a discount for purchased items, the method comprising providing a plurality of items to be purchased by a customer, applying a recursive discount scheme for determining available discounts for said plurality of items to be purchased, selecting a highest discount value from said available discounts for said plurality of items, and notifying said customer of said highest discount value for said plurality of items.

Abstract translation: 一种计算机实现的方法，用于确定购买物品的折扣，所述方法包括提供由客户购买的多个物品，应用递归折扣方案来确定所述多个待购买物品的可用折扣，选择最高折扣 从所述多个项目的所述可用折扣的价值，以及向所述客户通知所述多个项目的所述最高折扣值。

公开(公告)号：US20070109899A1

公开(公告)日：2007-05-17

申请号：US11335437

申请日：2006-01-18

Applicant: Lin-Shih Liu ,  Mark Chan

Inventor： Lin-Shih Liu ,  Mark Chan

IPC: G11C5/14

CPC classification number: H03K19/1776 ,  H03K19/17784

Abstract: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

公开(公告)号：US06236237B1

公开(公告)日：2001-05-22

申请号：US09258165

申请日：1999-02-25

Applicant: Myron W. Wong ,  Mark Chan

Inventor： Myron W. Wong ,  Mark Chan

IPC: H03K1901

CPC classification number: H03K19/0013

Abstract: An output buffer with feedback to a predriver circuit such that the effective size of the predriver buffers are momentarily adjusted to favor a particular transition (i.e., low-to-high or high-to-low). The delayed output selectively alters the input threshold characteristic of the predriver circuit to favor the appropriate transition. Thus, the time during which the output drivers are subject to a crowbar current is reduced over previous devices.

Abstract translation: 具有反馈给预驱动电路的输出缓冲器，使得暂时调整预驱动缓冲器的有效大小以有利于特定的转变（即从低到高或从高到低）。 延迟输出选择性地改变预驱动电路的输入阈值特性以有利于适当的转换。 因此，输出驱动器遭受撬棒电流的时间比以前的器件减少。

公开(公告)号：US20070113106A1

公开(公告)日：2007-05-17

申请号：US11282858

申请日：2005-11-17

Applicant: Lin-Shih Liu ,  Mark Chan

Inventor： Lin-Shih Liu ,  Mark Chan

IPC: G06F1/26

CPC classification number: G06F1/3225

Abstract: Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

Abstract translation: 提供具有存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 当加载配置数据时，存储器元件产生施加到可编程逻辑器件中的晶体管的栅极的输出信号以定制可编程逻辑。 为了确保可编程逻辑中的晶体管正确接通，在正常设备操作期间，存储器元件由提供的电源电平供电。 在数据加载操作期间，存储器元件的电源电平降低。 在加载期间降低存储元件电源电平增加了存储器元件的写入裕度。

公开(公告)号：US20070109017A1

公开(公告)日：2007-05-17

申请号：US11282437

申请日：2005-11-17

Applicant: Lin-Shih Liu ,  Mark Chan ,  Toan Do

Inventor： Lin-Shih Liu ,  Mark Chan ,  Toan Do

IPC: H03K19/177

CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。