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1.发明授权Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address 有权基于操作码和操作数检测逻辑上的非有效操作，并设置标志将后续指令中指定的地址解码为不同的地址公开(公告)号：US08880852B2
公开(公告)日：2014-11-04
申请号：US13281958
申请日：2011-10-26
CPC分类号： G06F9/00 , G06F9/30145 , G06F9/3016 , G06F9/30178 , G06F9/30181 , G06F9/34
摘要： A method, apparatus, and program product execute instructions of an instruction stream and detect logically non-significant operations in the instruction stream. Then, based on that detection, a target or source address of a subsequent instruction is adjusted. In some instances, doing so enables a greater number of addresses, e.g., registers, to be accessed in a given number of bit positions within an instruction format.
摘要翻译： 方法，装置和程序产品执行指令流的指令并且检测指令流中的逻辑上非有效操作。 然后，基于该检测，调整后续指示的目标或源地址。 在一些情况下，这样做使得能够在指令格式中的给定数量的位位置中访问更多数量的地址，例如寄存器。
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公开(公告)号：US08522254B2
公开(公告)日：2013-08-27
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译： 芯片上的网络的集成处理器块可编程以执行第一功能。 集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问 到片上存储器。
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3.发明申请Opcode Space Minimizing Architecture Utilizing Instruction Address to Indicate Upper Address Bits 有权操作码空间最小化使用指令地址来指示上位地址的架构公开(公告)号：US20120084535A1
公开(公告)日：2012-04-05
申请号：US12894697
申请日：2010-09-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/3016 , G06F9/30181 , G06F9/345 , G06F9/3824
摘要： Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the upper address bits of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.
摘要翻译： 由于现代微处理器内核中的寄存器数量和新指令的数量不断增加，指令编码中存在的地址宽度不断扩大，更少的指令操作码可用，使得更难于将现有架构的新指令添加到现有的架构中，而无需使用不正当的 具有诸如源破坏性操作等缺点的技巧。 所公开的发明利用专门的解码和地址计算硬件，其将指令地址的固定数目的最低有效位连接到包含在指令中的每个寄存器地址部分的高地址位，从而产生完整寄存器地址，而不是提供完整寄存器 指令中使用的每个寄存器的地址宽度。 这释放了其他指令的有价值的操作码空间，避免了编译器的复杂性。 这很好地与汇编语言中大多数循环展开的方式保持一致，独立操作在内存中彼此靠近。
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公开(公告)号：US20110321049A1
公开(公告)日：2011-12-29
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译： 芯片上的网络的集成处理器块可编程以执行第一功能。 集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问 到片上存储器。
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公开(公告)号：US10261793B2
公开(公告)日：2019-04-16
申请号：US13328185
申请日：2011-12-16
IPC分类号： G06F9/30
摘要： A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses.
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6.发明授权Processing core with speculative register preprocessing in unused execution unit cycles 有权在未使用的执行单位周期内处理具有推测寄存器预处理的内核公开(公告)号：US09195463B2
公开(公告)日：2015-11-24
申请号：US13307575
申请日：2011-11-30
CPC分类号： G06F9/383 , G06F7/499 , G06F9/30014 , G06F9/30025 , G06F9/3836 , G06F9/384 , G06F9/3875 , G06F9/3885
摘要： A method and circuit arrangement speculatively preprocess data stored in a register file during otherwise unused cycles in an execution unit, e.g., to prenormalize denormal floating point values stored in a floating point register file, to decompress compressed values stored in a register file, to decrypt encrypted values stored in a register file, or to otherwise preprocess data that is stored in an unprocessed form in a register file.
摘要翻译： 一种方法和电路装置在执行单元中的其他未使用的周期期间推测性地预处理存储在寄存器文件中的数据，例如，将存储在浮点寄存器文件中的非正常浮点值预正规化，以解压缩存储在寄存器堆中的压缩值，以解密 存储在寄存器文件中的加密值，或以其他方式预处理以未处理形式存储在寄存器文件中的数据。
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7.发明授权Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bits 有权操作码空间最小化结构，利用指令地址的最低有效部分作为高位寄存器地址位公开(公告)号：US09075599B2
公开(公告)日：2015-07-07
申请号：US12894697
申请日：2010-09-30
CPC分类号： G06F9/30098 , G06F9/3016 , G06F9/30181 , G06F9/345 , G06F9/3824
摘要： Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the most significant side of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.
摘要翻译： 由于现代微处理器内核中的寄存器数量和新指令的数量不断增加，指令编码中存在的地址宽度不断扩大，更少的指令操作码可用，使得更难于将现有架构的新指令添加到现有的架构中，而无需使用不正当的 具有诸如源破坏性操作等缺点的技巧。 所公开的发明利用专门的解码和地址计算硬件，其将指令地址的固定数量的最低有效位连接到包含在指令中的每个寄存器地址部分的最高有效侧，从而产生完整寄存器地址，而不是提供完整寄存器 指令中使用的每个寄存器的地址宽度。 这释放了其他指令的有价值的操作码空间，避免了编译器的复杂性。 这很好地与汇编语言中大多数循环展开的方式保持一致，独立操作在内存中彼此靠近。
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公开(公告)号：US20130185477A1
公开(公告)日：2013-07-18
申请号：US13352619
申请日：2012-01-18
IPC分类号： G06F12/00
CPC分类号： G06F11/263
摘要： A method includes receiving, from a processor, a first read request mapped including a first read request address to a first memory location of a register array and a second read request including a second read request address to a second memory location of a register array. The method includes assigning a first simulated time delay to the first read request and assigning a second simulated time delay to the second read request. The method includes, in response to a first elapsed time being equal to the first simulated time delay, outputting a first read request response including first data. The first elapsed time commences upon receipt of the first read request. The method includes, in response to a second elapsed time being equal to the second simulated time delay, outputting a second read request response including second data. The second elapsed time commences upon receipt of the second read request.
摘要翻译： 一种方法包括从处理器接收包括第一读取请求地址的第一读取请求到寄存器阵列的第一存储器位置以及包括第二读取请求地址的第二读取请求到寄存器阵列的第二存储器位置。 该方法包括将第一模拟时间延迟分配给第一读取请求并将第二模拟时间延迟分配给第二读取请求。 该方法包括响应于第一经过时间等于第一模拟时间延迟，输出包括第一数据的第一读请求响应。 第一次经过的时间在收到第一个读取请求后开始。 该方法包括响应于第二经过时间等于第二仿真时间延迟，输出包括第二数据的第二读请求响应。 第二个经过时间在收到第二个读取请求后开始。
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9.发明申请Redundant Execution of Instructions in Multistage Execution Pipeline During Unused Execution Cycles 失效在多个执行循环中执行多级执行管道中的指令冗余执行公开(公告)号：US20100042813A1
公开(公告)日：2010-02-18
申请号：US12191331
申请日：2008-08-14
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3869
摘要： A pipelined execution unit uses the bubbles that occur during execution to selectively repeat operations performed in one or more stages of a multistage execution pipeline to verify the results of such operations during otherwise unused execution cycles for the execution pipeline. Whenever a bubble follows a particular instruction within an execution pipeline, the result of an operation that is performed for that instruction by a particular stage of the execution pipeline may be stored, and the operation may be repeated by the stage in a subsequent execution cycle in which no productive operation would otherwise be performed due to the presence of the bubble. The results of the operations may then be compared and used to either verify the original result or identify a potential error in the execution of the instruction.
摘要翻译： 流水线执行单元使用在执行期间发生的气泡来选择性地重复在多级执行流水线的一个或多个阶段中执行的操作，以在执行流水线的另外未使用的执行周期期间验证这种操作的结果。 每当气泡遵循执行流水线中的特定指令时，可以存储由执行流水线的特定阶段对该指令执行的操作的结果，并且可以在后续执行周期中的阶段重复该操作， 否则由于存在气泡而不能进行生产操作。 然后可以将操作的结果进行比较并用于验证原始结果或识别指令执行中的潜在错误。
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公开(公告)号：US20100042812A1
公开(公告)日：2010-02-18
申请号：US12191337
申请日：2008-08-14
CPC分类号： G06F9/30181 , G06F9/3016
摘要： A circuit arrangement and method support data dependent instruction decoding, whereby instructions are decoded, in part, using decode data that is stored in operand registers identified by such instructions. An instruction may include an opcode and at least one operand that identifies a register. During execution of the instruction, the instruction is first decoded using the opcode, and then decode data stored in the operand register is retrieved and used to further decode the instruction, e.g., to select from among a plurality of operations or instruction types associated with the same opcode.
摘要翻译： 一种电路装置和方法支持数据相关指令解码，其中部分地使用存储在由这些指令识别的操作数寄存器中的解码数据来解码指令。 指令可以包括操作码和标识寄存器的至少一个操作数。 在执行指令期间，首先使用操作码解码指令，然后检索存储在操作数寄存器中的解码数据，并用于进一步解码指令，例如，从多个操作或与该指令相关联的指令类型中进行选择 相同的操作码
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