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公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译： 具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。 超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。 每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连 使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。
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公开(公告)号：US20110298788A1
公开(公告)日：2011-12-08
申请号：US12794207
申请日：2010-06-04
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06F7/483 , G06F7/5443
摘要： A method includes receiving packed data corresponding to pixel components to be processed at a graphics pipeline. The method includes unpacking the packed data to generate floating point numbers that correspond to the pixel components. The method also includes routing each of the floating point numbers to a separate lane of the graphics pipeline. Each of the floating point numbers are to be processed by multiplier units of the graphics pipeline.
摘要翻译： 一种方法包括在图形流水线处接收对应于要处理的像素分量的打包数据。 该方法包括打包打包数据以产生对应于像素分量的浮点数。 该方法还包括将每个浮点数路由到图形流水线的单独通道。 每个浮点数由图形管线的乘法器单元处理。
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公开(公告)号：US20110167296A1
公开(公告)日：2011-07-07
申请号：US12652360
申请日：2010-01-05
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0727
摘要： Register file soft error recovery including a system that includes a first register file and a second register file that mirrors the first register file. The system also includes an arithmetic pipeline for receiving data read from the first register file, and error detection circuitry to detect whether the data read from the first register file includes corrupted data. The system further includes error recovery circuitry to insert an error recovery instruction into the arithmetic pipeline in response to detecting the corrupted data. The inserted error recovery instruction replaces the corrupted data in the first register file with a copy of the data from the second register file.
摘要翻译： 注册文件软错误恢复，包括包含第一个寄存器文件和第二个寄存器文件的系统，该寄存器文件反映第一个寄存器文件。 该系统还包括用于接收从第一寄存器文件读取的数据的算术流水线，以及用于检测从第一寄存器堆中读取的数据是否包含损坏的数据的错误检测电路。 系统还包括错误恢复电路，以响应于检测到损坏的数据将错误恢复指令插入算术流水线。 插入的错误恢复指令用第二个寄存器文件的数据副本替换第一个寄存器文件中的损坏的数据。
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4.发明授权Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address 有权基于操作码和操作数检测逻辑上的非有效操作，并设置标志将后续指令中指定的地址解码为不同的地址公开(公告)号：US08880852B2
公开(公告)日：2014-11-04
申请号：US13281958
申请日：2011-10-26
CPC分类号： G06F9/00 , G06F9/30145 , G06F9/3016 , G06F9/30178 , G06F9/30181 , G06F9/34
摘要： A method, apparatus, and program product execute instructions of an instruction stream and detect logically non-significant operations in the instruction stream. Then, based on that detection, a target or source address of a subsequent instruction is adjusted. In some instances, doing so enables a greater number of addresses, e.g., registers, to be accessed in a given number of bit positions within an instruction format.
摘要翻译： 方法，装置和程序产品执行指令流的指令并且检测指令流中的逻辑上非有效操作。 然后，基于该检测，调整后续指示的目标或源地址。 在一些情况下，这样做使得能够在指令格式中的给定数量的位位置中访问更多数量的地址，例如寄存器。
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公开(公告)号：US08522254B2
公开(公告)日：2013-08-27
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译： 芯片上的网络的集成处理器块可编程以执行第一功能。 集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问 到片上存储器。
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6.发明申请Opcode Space Minimizing Architecture Utilizing Instruction Address to Indicate Upper Address Bits 有权操作码空间最小化使用指令地址来指示上位地址的架构公开(公告)号：US20120084535A1
公开(公告)日：2012-04-05
申请号：US12894697
申请日：2010-09-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/3016 , G06F9/30181 , G06F9/345 , G06F9/3824
摘要： Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the upper address bits of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.
摘要翻译： 由于现代微处理器内核中的寄存器数量和新指令的数量不断增加，指令编码中存在的地址宽度不断扩大，更少的指令操作码可用，使得更难于将现有架构的新指令添加到现有的架构中，而无需使用不正当的 具有诸如源破坏性操作等缺点的技巧。 所公开的发明利用专门的解码和地址计算硬件，其将指令地址的固定数目的最低有效位连接到包含在指令中的每个寄存器地址部分的高地址位，从而产生完整寄存器地址，而不是提供完整寄存器 指令中使用的每个寄存器的地址宽度。 这释放了其他指令的有价值的操作码空间，避免了编译器的复杂性。 这很好地与汇编语言中大多数循环展开的方式保持一致，独立操作在内存中彼此靠近。
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公开(公告)号：US20110321049A1
公开(公告)日：2011-12-29
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译： 芯片上的网络的集成处理器块可编程以执行第一功能。 集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问 到片上存储器。
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公开(公告)号：US08930432B2
公开(公告)日：2015-01-06
申请号：US13197894
申请日：2011-08-04
CPC分类号： G06F9/30014 , G06F7/483 , G06F9/3001 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3836 , G06F9/3889 , G06F2207/3824
摘要： A floating point execution unit is capable of selectively repurposing one or more adders in an exponent path of the floating point execution unit to perform fixed point addition operations, thereby providing fixed point functionality in the floating point execution unit.
摘要翻译： 浮点执行单元能够选择性地重新排列浮点执行单元的指数路径中的一个或多个加法器，以执行固定点加法运算，从而在浮点执行单元中提供固定点功能。
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公开(公告)号：US08629867B2
公开(公告)日：2014-01-14
申请号：US12794207
申请日：2010-06-04
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06F7/483 , G06F7/5443
摘要： A method includes receiving packed data corresponding to pixel components to be processed at a graphics pipeline. The method includes unpacking the packed data to generate floating point numbers that correspond to the pixel components. The method also includes routing each of the floating point numbers to a separate lane of the graphics pipeline. Each of the floating point numbers are to be processed by multiplier units of the graphics pipeline.
摘要翻译： 一种方法包括在图形流水线处接收对应于要处理的像素分量的打包数据。 该方法包括打包打包数据以产生对应于像素分量的浮点数。 该方法还包括将每个浮点数路由到图形流水线的单独通道。 每个浮点数由图形管线的乘法器单元处理。
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公开(公告)号：US20130159683A1
公开(公告)日：2013-06-20
申请号：US13328185
申请日：2011-12-16
CPC分类号： G06F9/30072 , G06F9/30018
摘要： A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses.
摘要翻译： 一种特定的方法包括在处理器处接收指令的指令和地址。 该方法还包括至少部分地基于确定地址在地址范围内来防止执行指令。
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