Universal serial bus controlled connect and disconnect
    1.
    发明授权
    Universal serial bus controlled connect and disconnect 有权
    通用串行总线控制连接和断开

    公开(公告)号:US06415342B1

    公开(公告)日:2002-07-02

    申请号:US09361952

    申请日:1999-07-27

    IPC分类号: G06F1300

    CPC分类号: G06F13/4072

    摘要: A device for connection to a Universal Serial Bus (USB) signals connection and disconnection from the bus without physically removing or reinserting the USB cable. The devices system controller controls the signaling so that connection or disconnection may be signaled in a variety of situations to accomplish certain tasks. Connection signaling may be delayed until power-up reset procedures are complete to prevent the device from being polled by the host. A disconnect then a connect may be signaled to help recover from certain error conditions. The same data lines may also be used for interfaces other than the USB bus. A switched connection from a USB data line through a pull-up resistor to a positive supply voltage. The switched connection is controlled by a logic function so that it will not be connected when the power supply on the USB cable is not present. The switched connection is also controlled by a logic signal that may be supplied by the USB device's system controller.

    摘要翻译: 用于连接到通用串行总线(USB)的设备将信号连接和断开总线,而无需物理移除或重新插入USB电缆。 设备系统控制器控制信令,从而可以在各种情况下发出连接或断开信号来完成某些任务。 连接信令可能会延迟,直到上电复位过程完成,以防止设备被主机轮询。 断开连接,可能会发出连接,以帮助从某些错误状况恢复。 相同的数据线也可以用于除USB总线以外的接口。 从USB数据线通过上拉电阻到正电源电压的切换连接。 开关式连接由逻辑功能控制,因此USB电缆上的电源不存在时不会连接。 开关式连接也由可由USB设备的系统控制器提供的逻辑信号控制。

    Configurable driver circuit and termination for a computer input/output
bus
    3.
    发明授权
    Configurable driver circuit and termination for a computer input/output bus 失效
    用于计算机输入/输出总线的可组态驱动电路和终端

    公开(公告)号:US5361005A

    公开(公告)日:1994-11-01

    申请号:US40815

    申请日:1993-03-31

    IPC分类号: H03K19/0185

    CPC分类号: H03K19/018585

    摘要: A configurable driver/termination circuit for use in a peripheral device connected to a computer input/output controller bus. The driver/termination circuit has the pull-up current source characteristics of a three-state driver and the pull-down current sink characteristics of a open collector driver. Logic circuit defines the operating mode. In a default mode, the driver/termination circuit can function in either open collector or three-state bus designs. The circuit mode is changed by command from a host computer to explicitly operate as an open collector driver/terminator, as a three-state driver, or as an inactive high impedance. Alternatively, peripheral devices automatically select the mode which minimizes data transmission errors.

    摘要翻译: 可配置的驱动器/终端电路,用于连接到计算机输入/输出控制器总线的外围设备。 驱动器/终端电路具有三态驱动器的上拉电流源特性和开路集电极驱动器的下拉电流吸收特性。 逻辑电路定义了工作模式。 在默认模式下,驱动器/终端电路可以采用集电极开路或三态总线设计。 电路模式通过来自主机的命令改变为显式地作为开路集电极驱动器/终端器,作为三态驱动器或作为非活动高阻抗来运行。 或者,外围设备自动选择最小化数据传输错误的模式。

    Selection apparatus and method
    5.
    发明授权
    Selection apparatus and method 有权
    选择装置及方法

    公开(公告)号:US06647436B1

    公开(公告)日:2003-11-11

    申请号:US09630522

    申请日:2000-08-02

    IPC分类号: G06F1314

    摘要: Two interfaces or operating modes are designed into the hardware and firmware. Selection between these two interfaces, or operating modes, is indicated by the position of a jumper on an IDE/ATAPI-style jumper block. A pull-up resistor and interface type detection signal are connected to a pin on the IDE/ATAPI-style jumper block associated with a jumper that is not monitored by the IDE/ATAPI master/slave selection detect (or other configuration) hardware or used to pull-down or pull-up another jumpered pin on the jumper block. When a jumper is placed between this pin, and a pin used to pull-up or pull-down another jumpered pin the interface type detection signal will be read as being at the pulled-up or pulled-down logic level, respectively. Otherwise, the IDE/ATAPI master/slave selection (or other configuration) detect hardware will function normally.

    摘要翻译: 在硬件和固件中设计了两种接口或操作模式。 这两个接口或操作模式之间的选择由IDE / ATAPI型跳线块上的跳线位置指示。 上拉电阻和接口类型检测信号连接到与未由IDE / ATAPI主/从选择检测(或其他配置)硬件或使用的监视器的跳线相关联的IDE / ATAPI型跳线块上的引脚 在跳线块上下拉或上拉另一个跳线针。 当该引脚和用于上拉或下拉另一个跨接引脚的引脚之间插入跳线时,接口类型检测信号将被分别读取为上拉或下拉逻辑电平。 否则,IDE / ATAPI主/从选择(或其他配置)检测硬件将正常运行。