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1.发明授权Power control apparatus and method for controlling a supply voltage for an associated circuit 有权用于控制相关电路的电源电压的功率控制装置和方法公开(公告)号：US08456140B2
公开(公告)日：2013-06-04
申请号：US12805146
申请日：2010-07-14
IPC分类号： G05F1/00
CPC分类号： G11C5/148
摘要： A power control apparatus for controlling a supply voltage for an associated circuit comprises a power input for receiving an input voltage and a power output for supplying the supply voltage to the circuit. A switch device is provided with a first terminal coupled to the power input, a second terminal coupled to the power output and a control terminal for receiving a sleep select signal. A control device selectively configures the switch device to act as either a power gating switch, in which the switch device is responsive to the sleep select signal to select whether or not to supply the input voltage to the power output; or a retention switch in which a voltage difference is formed between the power input and the power input and the switch device supplies a retention voltage to the power output, the retention voltage being different to the input voltage.
摘要翻译： 用于控制相关电路的电源电压的功率控制装置包括用于接收输入电压的电源输入和用于向电路供应电源电压的功率输出。 开关装置设置有耦合到电力输入的第一端子，耦合到功率输出的第二端子和用于接收睡眠选择信号的控制端子。 控制装置选择性地配置开关装置作为电源门控开关，其中开关装置响应于睡眠选择信号来选择是否将输入电压提供给功率输出; 或其中在电源输入和电源输入之间形成电压差并且开关器件向功率输出提供保持电压的保持开关，保持电压不同于输入电压。
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2.发明授权公开(公告)号：US08390328B2
公开(公告)日：2013-03-05
申请号：US13067184
申请日：2011-05-13
IPC分类号： H03K19/00
CPC分类号： H03K19/0013 , G06F17/5059 , G06F2217/62 , G06F2217/78 , G06F2217/84 , H03K19/0016
摘要： A clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The circuitry receives a clock signal, a clock enable signal having either an enable value or a disable value, and a power mode signal having either a low power value (indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down), or a functional mode value (indicating the plurality of synchronous elements are to be powered). A clock gating unit has logic circuitry that is configured to output the clock signal or the predetermined gated value depending upon the low power value and the functional mode value.
摘要翻译： 时钟选通电路被配置为接收时钟信号并输出包括时钟信号或预定门控值的输出信号。 电路接收时钟信号，具有使能值或禁用值的时钟使能信号，以及具有低功率值的功率模式信号（指示进入低功率模式，其中多个功率模式中的至少一部分 同步元件被供电以保持数据并且不被计时，并且多个同步元件的至少另一部分被断电）或功能模式值（指示多个同步元件被供电）。 时钟门控单元具有被配置为根据低功率值和功能模式值输出时钟信号或预定门控值的逻辑电路。
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公开(公告)号：US20120013319A1
公开(公告)日：2012-01-19
申请号：US12805146
申请日：2010-07-14
IPC分类号： G05F1/10
CPC分类号： G11C5/148
摘要： A power control apparatus for controlling a supply voltage for an associated circuit comprises a power input for receiving an input voltage and a power output for supplying the supply voltage to the circuit. A switch device is provided with a first terminal coupled to the power input, a second terminal coupled to the power output and a control terminal for receiving a sleep select signal. A control device selectively configures the switch device to act as either a power gating switch, in which the switch device is responsive to the sleep select signal to select whether or not to supply the input voltage to the power output; or a retention switch in which a voltage difference is formed between the power input and the power input and the switch device supplies a retention voltage to the power output, the retention voltage being different to the input voltage.
摘要翻译： 用于控制相关电路的电源电压的功率控制装置包括用于接收输入电压的电源输入和用于向电路供应电源电压的功率输出。 开关装置设置有耦合到电力输入的第一端子，耦合到功率输出的第二端子和用于接收睡眠选择信号的控制端子。 控制装置选择性地配置开关装置作为电源门控开关，其中开关装置响应于睡眠选择信号来选择是否将输入电压提供给功率输出; 或其中在电源输入和电源输入之间形成电压差并且开关器件向功率输出提供保持电压的保持开关，保持电压不同于输入电压。
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公开(公告)号：US07745275B2
公开(公告)日：2010-06-29
申请号：US12232107
申请日：2008-09-10
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/76816 , H01L27/0207 , H01L29/66545
摘要： A method of forming an integrated circuit 68 provides over a diffusion region 28 on a substrate 26 a gate electrode 36. A source electrode is provided by a source local interconnect conductor 30 and a drain electrode is provided by a drain local interconnect conductor 32. An insulator layer 38 is formed over these electrodes and respective electrode openings are formed through the insulator layer 38 so as to provide electrical connection to a Metal1 layer 46, 48, 50. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer 38 and accordingly short circuit a gate insulator layer 34 provided between the diffusion region 28 and the gate electrode 36. Thus, the gate opening may be positioned over the diffusion region 28. Double patterning followed by separate etching steps for the gate opening and the source/drain opening may be used to control the gate opening depth and permit the gate contact to be position overlying the diffusion region.
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公开(公告)号：US20100115484A1
公开(公告)日：2010-05-06
申请号：US12289771
申请日：2008-11-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries.
摘要翻译： 提供了一种生成集成电路的布局的方法，该方法包括以下步骤：提供表示电路元件和电路元件之间的连接的功能数据，提供限定多个标准单元的单元库，每个标准单元代表一个电位 用于形成集成电路的组件，提供指示标准单元的边界的兼容性的兼容性信息，以及根据功能数据和兼容性信息生成标准单元的放置以产生布局，使得没有邻接单元具有不兼容 边界
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公开(公告)号：US20100100861A1
公开(公告)日：2010-04-22
申请号：US12289159
申请日：2008-10-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A layout for an integrated circuit includes standard cells 6 positioned at standard cell sites 4. Programmable cells 10 are positioned at programmable fill sites 8 which have a size sufficient to accommodate the programmable cells 10 and are not occupied by standard cells 6. The position of these programmable sites 8 is recorded in site data as part of the layout data associated with the layout 2. Empty standard cell sites 4 remaining after standard cells 6 and programmable cells 10 have been placed are filled with standard fill cells 12. The boundaries of the programmable cells 10 are not constrained other than by alignment with standard cell sites 4. This permits a high density of programmable fill sites 8 and programmable cells 10 to be achieved. When it is desired to replace a programmable cell 10 with a programmed cell 38′ the programmable cells 10 are all deleted from the layout and then the required programmed cells 38′ are subject to an automated placement algorithm to place them where appropriate for their function. The remaining empty programmable fill sites 8 are then refilled with programmable cells 10. Finally, routing algorithms to connect to and from the newly introduced programmed cells 38′ are executed to connect those program cells 38′ up to the other points within the integrated circuit layout 2 required.
摘要翻译： 集成电路的布局包括位于标准单元位置处的标准单元6.可编程单元10位于可编程填充位置8处，其具有足以容纳可编程单元10的尺寸，并且不被标准单元6占据。位置 这些可编程位置8被记录在站点数据中，作为与布局2相关联的布局数据的一部分。已经放置了标准单元6和可编程单元10之后剩余的空的标准单元站点4填充有标准填充单元12.边界 可编程单元10不受与标准单元位置4对准的约束。这允许实现高密度的可编程填充位置8和可编程单元10。 当希望用编程单元38'替换可编程单元10时，可编程单元10都从布局中删除，然后所需的编程单元38'经受自动放置算法，以将它们放置在适合其功能的位置。 剩余的空可编程填充位置8然后用可编程单元10重新填充。最后，执行用于连接到新引入的编程单元38'和从新引入的编程单元38'的路由算法，以将那些编程单元38'连接到集成电路布局内的其他点 2需要。
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公开(公告)号：US20100060321A1
公开(公告)日：2010-03-11
申请号：US12232187
申请日：2008-09-11
IPC分类号： H03K19/096 , H03K3/289 , H03K3/037
CPC分类号： G11C7/1078 , G11C7/1087 , G11C19/00
摘要： State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 12 is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry 2 is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry 2 when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.
摘要翻译： 描述了状态存储电路，其包括在其功能输入端具有三态反相器电路2的主 - 从锁存器和用于插入扫描数据的三态扫描信号插入电路12。 三态扫描信号插入电路12由第一时钟信号nclk和第二时钟信号bclk控制。 三态逆变器电路2由第三时钟信号nfclk和第四时钟信号flck控制。 时钟发生电路将第三和第四时钟信号保持在固定值，其在扫描模式下将三态反相器电路2三态化。 这将扫描控制逻辑从包括三态反相器电路的功能路径移动到时钟控制电路中。
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公开(公告)号：US08824215B2
公开(公告)日：2014-09-02
申请号：US13363623
申请日：2012-02-01
IPC分类号： G11C7/10
CPC分类号： G11C7/065 , G11C7/12 , G11C2207/2245
摘要： A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.
摘要翻译： 用于接收和保存数据值的数据存储电路包括：输入级，被配置为响应于预充电阶段改变为评估阶段并且在评估阶段期间保持数据值来接收数据值。 输出级具有用于保持该值的输出锁存元件，用于更新输出锁存元件的两个开关元件和输出。 开关装置各自由来自双数据线的相应信号控制，其中响应于输入级中保持的数据值为逻辑1，第一开关装置用指示逻辑1的值更新输出锁存元件，并且 响应于保持在输入级中的数据值为逻辑0，第二开关器件用指示逻辑零的值更新输出锁存元件。
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公开(公告)号：US20130064019A1
公开(公告)日：2013-03-14
申请号：US13363623
申请日：2012-02-01
CPC分类号： G11C7/065 , G11C7/12 , G11C2207/2245
摘要： A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.
摘要翻译： 用于接收和保存数据值的数据存储电路包括：输入级，被配置为响应于预充电阶段改变为评估阶段并且在评估阶段期间保持数据值来接收数据值。 输出级具有用于保持该值的输出锁存元件，用于更新输出锁存元件的两个开关元件和输出。 开关装置各自由来自双数据线的相应信号控制，其中响应于输入级中保持的数据值为逻辑1，第一开关装置用指示逻辑1的值更新输出锁存元件，并且 响应于保持在输入级中的数据值为逻辑0，第二开关器件用指示逻辑零的值更新输出锁存元件。
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公开(公告)号：US08136072B2
公开(公告)日：2012-03-13
申请号：US12289771
申请日：2008-11-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries.
摘要翻译： 提供了一种生成集成电路的布局的方法，该方法包括以下步骤：提供表示电路元件和电路元件之间的连接的功能数据，提供限定多个标准单元的单元库，每个标准单元代表一个电位 用于形成集成电路的组件，提供指示标准单元的边界的兼容性的兼容性信息，以及根据功能数据和兼容性信息生成标准单元的放置以产生布局，使得没有邻接单元具有不兼容 边界
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