Operation state display apparatus
    1.
    发明授权
    Operation state display apparatus 失效
    操作状态显示装置

    公开(公告)号:US3987432A

    公开(公告)日:1976-10-19

    申请号:US548926

    申请日:1975-02-11

    IPC分类号: G07C3/00 G06K15/20

    CPC分类号: G07C3/00

    摘要: An operation state display apparatus is disclosed having a first memory device for memorizing a time from an operation initiation reference time when an input signal is switched from the ON state to the OFF state or from the OFF state to the ON state wherein each input signal is for each operation state of a controlled object. A second memory device is provided for memorizing a last time of the OFF state or the ON state after switching from the ON state to the OFF state or from the OFF state to the ON state as the time from the operation initiation reference time. The apparatus includes a display device for displaying the operation state of the controlled object depending upon the data of the first and second memories in the form of a time chart.

    摘要翻译: 公开了一种操作状态显示装置,其具有第一存储装置,用于当输入信号从ON状态切换到OFF状态或从OFF状态切换到ON状态时从操作开始基准时间存储时间,其中每个输入信号为 对于受控对象的每个操作状态。 提供了第二存储装置,用于在从操作开始基准时间开始的时间之后,将从ON状态切换到OFF状态或从OFF状态切换到ON状态的最后一次关闭状态或ON状态。 该装置包括显示装置,用于根据时间图形式的第一和第二存储器的数据显示受控对象的操作状态。

    Operation state display apparatus
    4.
    发明授权
    Operation state display apparatus 失效
    操作状态显示装置

    公开(公告)号:US4107663A

    公开(公告)日:1978-08-15

    申请号:US555597

    申请日:1975-03-05

    IPC分类号: G07C3/00 G06F3/14

    CPC分类号: G07C3/00

    摘要: An operation state display apparatus includes a counter for receiving input signals which respectively represent the individual operation states of a controlled object and for counting the duration time of at least one of the ON and OFF state of the input signal. A memory device is provided for memorizing the period of time lapse from an operation initiation reference time when the input signal goes from the OFF state to the ON state or vice versa. A display device is provided for displaying in the form of a time chart the operation state of the controlled object according to the data of the counter and of the memory device. The reference operation state of the controlled object can also be displayed on the display device.

    摘要翻译: 操作状态显示装置包括:计数器,用于接收分别表示受控对象的各个操作状态的输入信号,并计数输入信号的ON和OFF状态中的至少一个的持续时间。 提供存储装置,用于存储从输入信号从OFF状态变为ON状态的操作开始基准时间经过的时间段,反之亦然。 提供一种显示装置,用于根据计数器和存储装置的数据以时间图的形式显示受控对象的操作状态。 受控对象的参考操作状态也可以显示在显示装置上。

    Operation state monitoring apparatus
    5.
    发明授权
    Operation state monitoring apparatus 失效
    运行状态监控装置

    公开(公告)号:US4035786A

    公开(公告)日:1977-07-12

    申请号:US562869

    申请日:1975-03-27

    摘要: An operation state monitoring apparatus for monitoring an operation state of a controlled object is disclosed. The apparatus compares actual operation state data of the controlled object with reference operation state data of the controlled object read out from a reference operation state data memory and sets desirable data selected from the actual operation state data to the reference operation state data memory as the reference operation state data.

    摘要翻译: 公开了一种用于监视受控对象的操作状态的操作状态监视装置。 该设备将受控对象的实际操作状态数据与从参考操作状态数据存储器读出的受控对象的参考操作状态数据进行比较,并将从实际操作状态数据中选择的所需数据设置为参考操作状态数据存储器作为参考 操作状态数据。

    Digital logical sequence controller
    6.
    发明授权
    Digital logical sequence controller 失效
    数字逻辑序列控制器

    公开(公告)号:US3944987A

    公开(公告)日:1976-03-16

    申请号:US467142

    申请日:1974-05-06

    IPC分类号: G05B19/05 G05B11/01 G06F9/00

    CPC分类号: G05B19/05 G05B2219/15105

    摘要: A sequence controller of the digital logical circuit type, comprising a sequence program part and a processing circuit, wherein the desired sequence instruction is read from the sequence program part, and the sequence is processed and controlled by the processing circuit. A certain definite level is set at a branch point in an equivalent sequential circuit according to the path along which a signal of the sequential circuit is transmitted. This level and the on-off state of the branch point are stored in a memory. The given data are processed and controlled through the sequence program part and the memory.

    摘要翻译: 数字逻辑电路类型的序列控制器,包括序列程序部分和处理电路,其中从序列程序部分读取期望的序列指令,并且该序列由处理电路进行处理和控制。 根据发送顺序电路的信号的路径,在等效时序电路的分支点设定一定的限定电平。 该级别和分支点的开 - 关状态存储在存储器中。 给定的数据通过序列程序部分和存储器进行处理和控制。