公开(公告)号：US5194764A

公开(公告)日：1993-03-16

申请号：US627058

申请日：1990-12-13

申请人： Junji Yano ,  Tsukasa Miyawaki ,  Masami Atoh ,  Masakazu Gotou ,  Masakazu Iwashita ,  Michio Kaji

发明人： Junji Yano ,  Tsukasa Miyawaki ,  Masami Atoh ,  Masakazu Gotou ,  Masakazu Iwashita ,  Michio Kaji

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0948

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/108

摘要： A data output buffer circuit for a semiconductor integrated circuit has a plurality of output buffer circuits. Each output buffer circuit has an input terminal for receiving input data and an output buffer having first and second switching circuits serially connected between two high and low power source terminals. Each of the first and second switching circuits has a control terminal for turning on and off each of the first and second switching circuits upon receipt of a control signal at the control terminals. A timing signal input terminal receives a timing signal with which the output buffer circuit operates in synchronism. A timing switch connects the next stage of the input terminal and is turned on by the timing signal. A delay signal is connected between the timing switch means and the control terminals of the first and second switching circuits and delays the input data from the input terminal and transmits the delayed input data to the control terminals of the first and second switching circuits. The delay time of the delay circuit of one of the output buffer circuits is different from the delay time of another of the output buffer circuits. An output terminal connects to the interconnection between the first and second switching circuits.