公开(公告)号：US5194764A

公开(公告)日：1993-03-16

申请号：US627058

申请日：1990-12-13

申请人： Junji Yano ,  Tsukasa Miyawaki ,  Masami Atoh ,  Masakazu Gotou ,  Masakazu Iwashita ,  Michio Kaji

发明人： Junji Yano ,  Tsukasa Miyawaki ,  Masami Atoh ,  Masakazu Gotou ,  Masakazu Iwashita ,  Michio Kaji

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0948

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/108

摘要： A data output buffer circuit for a semiconductor integrated circuit has a plurality of output buffer circuits. Each output buffer circuit has an input terminal for receiving input data and an output buffer having first and second switching circuits serially connected between two high and low power source terminals. Each of the first and second switching circuits has a control terminal for turning on and off each of the first and second switching circuits upon receipt of a control signal at the control terminals. A timing signal input terminal receives a timing signal with which the output buffer circuit operates in synchronism. A timing switch connects the next stage of the input terminal and is turned on by the timing signal. A delay signal is connected between the timing switch means and the control terminals of the first and second switching circuits and delays the input data from the input terminal and transmits the delayed input data to the control terminals of the first and second switching circuits. The delay time of the delay circuit of one of the output buffer circuits is different from the delay time of another of the output buffer circuits. An output terminal connects to the interconnection between the first and second switching circuits.

公开(公告)号：US5936473A

公开(公告)日：1999-08-10

申请号：US964923

申请日：1997-11-05

申请人： Naoki Taniguchi ,  Kenjiro Kanayama ,  Tsukasa Miyawaki ,  Hidekazu Saito

发明人： Naoki Taniguchi ,  Kenjiro Kanayama ,  Tsukasa Miyawaki ,  Hidekazu Saito

IPC分类号： G06F15/78 ,  G06F1/04 ,  H03B5/32 ,  H03B5/36 ,  H03L3/00 ,  H03L7/095

CPC分类号： H03B5/36 ,  H03L3/00 ,  Y10S331/02 ,  Y10S331/03

摘要： An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.

摘要翻译： 当将低于外部振荡器的固有频率的频率提供给微型计算机时，振荡电路停止外部振荡器的振荡以减少消耗的电流。 PLL电路37从由振荡电路1输出的第一时钟23产生第二时钟45.当产生第二时钟45时，PLL锁定信号47从第一电平变为第二电平。 当PLL锁定信号47处于第二电平时，选择器39将第二时钟45输出为内部时钟13。 当PLL锁定信号47处于第二电平时，停止振荡器9的操作。