公开(公告)号：US08050100B2

公开(公告)日：2011-11-01

申请号：US12697505

申请日：2010-02-01

申请人： Masami Hanyu ,  Junichi Suzuki ,  Junichi Yamashita

发明人： Masami Hanyu ,  Junichi Suzuki ,  Junichi Yamashita

IPC分类号： G11C16/28

CPC分类号： G11C16/28

摘要： A non-volatile semiconductor memory device includes a sense amplifier, first and second bit lines that are connected to the sense amplifier, a first memory cell column that is connected to the first bit line, the first memory cell column being formed by a plurality of MONOS type transistors, a first constant current source that is connected to the second bit line, the first constant current source generating a reference current for the first memory cell column, and a first switch that is provided between the first constant current source and the second bit line, the first switch being formed by a MONOS type transistor.

摘要翻译： 非易失性半导体存储器件包括读出放大器，连接到读出放大器的第一和第二位线，连接到第一位线的第一存储器单元列，第一存储单元列由多个 MONOS型晶体管，连接到第二位线的第一恒定电流源，产生第一存储单元列的参考电流的第一恒定电流源和设置在第一恒定电流源和第二恒定电流源之间的第一开关， 第一开关由MONOS型晶体管形成。

公开(公告)号：US20100208525A1

公开(公告)日：2010-08-19

申请号：US12697505

申请日：2010-02-01

申请人： Masami HANYU ,  Junichi SUZUKI ,  Junichi YAMASHITA

发明人： Masami HANYU ,  Junichi SUZUKI ,  Junichi YAMASHITA

IPC分类号： G11C16/06

CPC分类号： G11C16/28

摘要： A non-volatile semiconductor memory device includes a sense amplifier, first and second bit lines that are connected to the sense amplifier, a first memory cell column that is connected to the first bit line, the first memory cell column being formed by a plurality of MONOS type transistors, a first constant current source that is connected to the second bit line, the first constant current source generating a reference current for the first memory cell column, and a first switch that is provided between the first constant current source and the second bit line, the first switch being formed by a MONOS type transistor.

摘要翻译： 非易失性半导体存储器件包括读出放大器，连接到读出放大器的第一和第二位线，连接到第一位线的第一存储器单元列，第一存储单元列由多个 MONOS型晶体管，连接到第二位线的第一恒定电流源，产生第一存储单元列的参考电流的第一恒定电流源和设置在第一恒定电流源与第二恒定电流源之间的第一开关， 第一开关由MONOS型晶体管形成。

公开(公告)号：US6094392A

公开(公告)日：2000-07-25

申请号：US393807

申请日：1999-09-10

申请人： Satoshi Utsugi ,  Masami Hanyu ,  Tadahiko Sugibayashi

发明人： Satoshi Utsugi ,  Masami Hanyu ,  Tadahiko Sugibayashi

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C7/12 ,  G11C7/18

摘要： A plurality of bit line pairs are provided in a semiconductor memory device. A plurality of memory cells are connected to the first bit line pairs. Also, in the semiconductor memory device, there are provided a first sense amplifier, a second bit line pair and a second sense amplifier. The first sense amplifier reads and amplifies a potential difference between the first bit line pair. A signal output from the first sense amplifier is transmitted to the second bit line pair. The second sense amplifier amplifies a potential difference between the second bit line pair. A precharge circuit is built in the second sense amplifier. The first bit line pairs are precharged by the precharge circuit.

摘要翻译： 多个位线对设置在半导体存储器件中。 多个存储单元连接到第一位线对。 此外，在半导体存储器件中，提供了第一读出放大器，第二位线对和第二读出放大器。 第一读出放大器读取并放大第一位线对之间的电位差。 从第一读出放大器输出的信号被发送到第二位线对。 第二读出放大器放大第二位线对之间的电位差。 在第二读出放大器中内置预充电电路。 第一位线对被预充电电路预充电。

公开(公告)号：US5953275A

公开(公告)日：1999-09-14

申请号：US128740

申请日：1998-08-04

申请人： Tadahiko Sugibayashi ,  Satoshi Utsugi ,  Masami Hanyu

发明人： Tadahiko Sugibayashi ,  Satoshi Utsugi ,  Masami Hanyu

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/18

摘要： A semiconductor dynamic random access memory device has first open bit lines arranged in parallel and second open bit lines respectively paired with the first open bit lines so as to form bit line pairs and a sense amplifier shared between the bit line pairs so as to increase the magnitude of a potential difference indicative of a data bit sequentially supplied from the bit line pairs, and either high or low level indicative of the data bit is supplied to both first and second bit lines of the selected bit line pair upon completion of the sense amplification, thereby equalizing electric influence on the adjacent open bit lines.

摘要翻译： 半导体动态随机存取存储器件具有并行布置的第一开路位线和分别与第一开路位线配对的第二开路位线，以便形成位线对和在位线对之间共享的读出放大器，以便增加 指示从位线对顺序提供的数据位的电位差的大小，以及指示数据位的高电平或低电平在完成感测放大后被提供给所选位线对的第一和第二位线 从而均衡对相邻打开位线的电影响。