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公开(公告)号：US6094392A
公开(公告)日：2000-07-25
申请号：US393807
申请日：1999-09-10
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , G11C7/18 , G11C11/401 , G11C7/00
摘要： A plurality of bit line pairs are provided in a semiconductor memory device. A plurality of memory cells are connected to the first bit line pairs. Also, in the semiconductor memory device, there are provided a first sense amplifier, a second bit line pair and a second sense amplifier. The first sense amplifier reads and amplifies a potential difference between the first bit line pair. A signal output from the first sense amplifier is transmitted to the second bit line pair. The second sense amplifier amplifies a potential difference between the second bit line pair. A precharge circuit is built in the second sense amplifier. The first bit line pairs are precharged by the precharge circuit.
摘要翻译： 多个位线对设置在半导体存储器件中。 多个存储单元连接到第一位线对。 此外，在半导体存储器件中，提供了第一读出放大器，第二位线对和第二读出放大器。 第一读出放大器读取并放大第一位线对之间的电位差。 从第一读出放大器输出的信号被发送到第二位线对。 第二读出放大器放大第二位线对之间的电位差。 在第二读出放大器中内置预充电电路。 第一位线对被预充电电路预充电。
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2.发明授权Semiconductor memory device having sense amplifiers shared between open bit line less affected by adjacent ones 失效半导体存储器件具有在相邻的较少受影响的开放位线之间共享的读出放大器
公开(公告)号：US5953275A
公开(公告)日：1999-09-14
申请号：US128740
申请日：1998-08-04
IPC分类号： G11C11/401 , G11C7/06 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4091 , G11C11/4097 , G11C7/18
摘要： A semiconductor dynamic random access memory device has first open bit lines arranged in parallel and second open bit lines respectively paired with the first open bit lines so as to form bit line pairs and a sense amplifier shared between the bit line pairs so as to increase the magnitude of a potential difference indicative of a data bit sequentially supplied from the bit line pairs, and either high or low level indicative of the data bit is supplied to both first and second bit lines of the selected bit line pair upon completion of the sense amplification, thereby equalizing electric influence on the adjacent open bit lines.
摘要翻译： 半导体动态随机存取存储器件具有并行布置的第一开路位线和分别与第一开路位线配对的第二开路位线，以便形成位线对和在位线对之间共享的读出放大器，以便增加 指示从位线对顺序提供的数据位的电位差的大小，以及指示数据位的高电平或低电平在完成感测放大后被提供给所选位线对的第一和第二位线 从而均衡对相邻打开位线的电影响。
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公开(公告)号：US5596542A
公开(公告)日：1997-01-21
申请号：US536189
申请日：1995-09-29
IPC分类号： H01L21/66 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/408 , G11C11/413 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C29/835 , G11C11/408 , G11C11/4087 , G11C8/10 , G11C8/12 , G11C8/14
摘要： In a semiconductor memory device including: a plurality of sub word lines, a plurality of sub word decoders each connected to one of the sub word lines, a plurality of pairs of main word lines each pair connected to a number of the sub word decoders, and a plurality of main word decoders each connected to one of the pairs of main word lines, each of the main word decoders sets voltages at a respective pair of the pairs of main word lines different from each other in a selection mode and sets the voltages at a respective pair of the pairs of main word lines the same as each other in a non-selection mode.
摘要翻译： 一种半导体存储器件，包括：多个子字线，多个子字解码器，每个子字解码器各自连接到一个子字线，多对主字线对，每对连接到多个子字解码器， 以及多个主字解码器，每个主字解码器连接到一对主字线中的每一个，每个主字解码器在选择模式下设置彼此不同的一对主字线对的电压，并将电压 在非选择模式下，相应的一对主字线彼此相同。
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4.发明授权Low power consumption semiconductor dynamic random access memory device by reusing residual electric charge on bit line pairs 失效低功耗半导体动态随机存取存储器件通过重新使用位线对上的残留电荷
公开(公告)号：US5631872A
公开(公告)日：1997-05-20
申请号：US658210
申请日：1996-06-04
IPC分类号： G11C11/401 , G11C11/406 , G11C11/4074 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4074 , G11C11/406 , G11C11/4094
摘要： A data refresh is indispensable for a semiconductor dynamic random access memory device, and electric charges are recycled from bit line pairs for a row of memory cell arrays to power supply lines for bit line drivers associated with the next row of memory cell arrays and from bit line pairs for the next row of memory cell arrays to power supply lines for the row of memory cell arrays, thereby reducing power consumption in the data refresh.
摘要翻译： 数据刷新对于半导体动态随机存取存储器件是不可缺少的，并且电荷从一行存储单元阵列的位线对再循环到与下一行存储单元阵列相关联的位线驱动器的电源线 用于下一行存储单元阵列的线对，用于为行存储单元阵列供电线，从而降低数据刷新中的功耗。
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公开(公告)号：US08503222B2
公开(公告)日：2013-08-06
申请号：US13144480
申请日：2010-01-21
申请人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
发明人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , H01L43/08 , H03K19/1776 , H03K19/1778 , H03K19/18 , H03K19/20
摘要： A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.
摘要翻译： 非易失性逻辑电路包括输入部分，控制部分和输出部分。 输入部具有垂直的磁各向异性，并具有磁化状态可变的铁磁层。 控制部分包括铁磁层。 输出部分设置在输入部分和控制部分的附近，并且包括磁化状态可变的磁性隧道结元件。 基于磁化状态改变输入部的磁化状态。 输出部分的磁性隧道结元件的磁化状态基于控制部分的铁磁材料的磁化状态和输入部分的铁磁材料的磁化状态而改变。
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公开(公告)号：US08477528B2
公开(公告)日：2013-07-02
申请号：US12443349
申请日：2007-09-25
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01L43/08
摘要： A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization inversion region 13 has a magnetization whose orientation is invertible and overlaps the pinned layer 30. The first magnetization fixed region 11 is connected with a first boundary B1 in the magnetization inversion region 13 and a magnetization orientation is fixed on a first direction. The second magnetization fixed region 12 is connected with a second boundary B2 in magnetization inversion region 13 and a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.
摘要翻译： 磁存储单元1设置有磁记录层10，磁记录层10是铁磁层，和通过非磁性层20与磁记录层10连接的钉扎层30.磁记录层10具有磁化反转区域13， 第一磁化固定区域11和第二磁化固定区域12.磁化反转区域13具有其取向可反转并与被钉扎层30重叠的磁化。第一磁化固定区域11与磁化反转中的第一边界B1连接 区域13和磁化取向在第一方向固定。 第二磁化固定区域12与磁化反转区域13中的第二边界B2连接，并且磁化取向固定在第二方向上。 第一方向和第二方向彼此相反。
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公开(公告)号：US08254157B2
公开(公告)日：2012-08-28
申请号：US12593423
申请日：2008-01-17
申请人： Tadahiko Sugibayashi
发明人： Tadahiko Sugibayashi
CPC分类号： G11C13/0007 , G11C7/04 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , H01L27/101
摘要： A semiconductor integrated circuit includes: an oxide resistance change element, a constant current source circuit supplying a write current to the oxide resistance change element, and a voltage clamper clamping a voltage in a path in which a write current flows. The voltage clamper is arranged in parallel with the path between the constant current source circuit and the oxide resistance change element.
摘要翻译： 半导体集成电路包括：氧化物电阻变化元件，向氧化物电阻变化元件提供写入电流的恒定电流源电路，以及夹持写入电流流动的路径中的电压的电压钳位器。 电压钳位器与恒流源电路和氧化物电阻变化元件之间的路径平行布置。
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公开(公告)号：US08243502B2
公开(公告)日：2012-08-14
申请号：US12747951
申请日：2008-11-19
IPC分类号： G11C11/00
CPC分类号： G11C11/18 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01L27/226 , H01L43/08 , H03K3/45
摘要： A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要翻译： 非易失性锁存电路包括：锁存电路; 第一磁阻元件和第二磁阻元件; 和电流供应部分。 锁存电路暂时保存数据。 第一磁阻元件和第二磁阻元件中的每一个包括层叠有绝缘膜的第一磁性层和第二磁性层。 电流供应部分基于锁存电路的状态互补地改变第一磁阻元件和第二磁阻元件的磁化状态。 第一磁阻元件的第一磁性层和第二磁阻元件的第一磁性层彼此串联连接。锁存电路具有将对应于磁化状态的数据带入由锁存电路保持的数据的功能。
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公开(公告)号：US07916520B2
公开(公告)日：2011-03-29
申请号：US11574121
申请日：2005-08-19
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C11/15 , H01L43/08 , Y10S977/935
摘要： A memory cell is used which includes a plurality of magneto-resistive elements and a plurality of laminated ferrimagnetic structure substances. The plurality of the magneto-resistive elements are placed corresponding to respective positions where a plurality of first wirings extended in a first direction intersects with a plurality of second wirings extended in a second direction which is substantially perpendicular to the first direction. The plurality of the laminated ferrimagnetic structure substances corresponds to the plurality of the magneto-resistive elements, respectively, is placed to have a distance of a predetermined range from the respective plurality of the magneto-resistive elements, and has a laminated ferrimagnetic structure. The magneto-resistive element includes a free layer having a laminated ferrimagnetic structure, a fixed layer, and a nonmagnetic layer interposed between the free layer and the fixed layer.
摘要翻译： 使用包括多个磁阻元件和多个叠层铁磁结构物质的存储单元。 多个磁阻元件对应于在第一方向上延伸的多个第一布线与基本上垂直于第一方向的第二方向延伸的多个第二布线相对应的相应位置放置。 多个叠层铁氧体结构物质分别对应于多个磁阻元件，放置成距离相应的多个磁阻元件具有预定范围的距离，并具有叠层铁磁结构。 磁阻元件包括层叠的铁磁结构，固定层和插入在自由层和固定层之间的非磁性层的自由层。
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10.发明授权Resistance change semiconductor memory device and method of reading data with a first and second switch circuit 有权电阻变化半导体存储器件以及利用第一和第二开关电路读取数据的方法公开(公告)号：US07885131B2
公开(公告)日：2011-02-08
申请号：US11815325
申请日：2006-02-01
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C7/02 , G11C7/062 , G11C7/14 , G11C11/4091 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.
摘要翻译： 本发明的半导体存储器件包括存储器阵列和读取所选择的单元的数据的读取电路。 存储器阵列包括多个存储器单元和参考单元，每个存储器单元具有存储元件，该存储元件基于电阻值的变化存储数据。 读取电路包括：电压比较单元，将来自所选择的单元的检测电流的值与来自参考单元的参考电流对应的值进行比较; 第一个开关 和第二开关。 第一和第二开关都被提供在解码器的后续阶段，并且在电压比较单元的前一级提供。 第二开关电路将对应于感测电流的值的输入控制到电压比较单元，而第一开关电路将对应于参考电流的值的输入控制到电压比较单元。
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