公开(公告)号：US08697531B2

公开(公告)日：2014-04-15

申请号：US13459305

申请日：2012-04-30

申请人： Masashi Shima

发明人： Masashi Shima

IPC分类号： H01L21/02 ,  H01L21/70 ,  H01L21/336 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

摘要： A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material, a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

摘要翻译： 半导体器件包括具有突起的硅衬底，形成在硅衬底的突起的上表面上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在硅衬底上的源极/漏极区域 所述第一侧壁形成在所述硅衬底的所述突起的侧表面上，所述第一侧壁包含绝缘材料，所述第二侧壁形成在所述第一侧壁上，所述第二侧壁具有底部 所述第二侧壁包含比所述硅基板的杨氏模量大的杨氏模量的材料，以及形成在所述栅电极和所述第二侧壁上的应力膜。

公开(公告)号：US08686501B2

公开(公告)日：2014-04-01

申请号：US12893297

申请日：2010-09-29

申请人： Masashi Shima

发明人： Masashi Shima

IPC分类号： H01L29/78 ,  H01L29/36

CPC分类号： H01L29/0653 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device includes: a p-type active region; a gate electrode traversing the active region; an n-type LDD region having a first impurity concentration and formed from a drain side region to a region under the gate electrode; a p-type channel region having a second impurity concentration and formed from a source side region to a region under the gate electrode to form an overlap region with the LDD region under the gate electrode, the channel region being shallower than the LDD region; an n-type source region formed outside the gate electrode; and an n+-type drain region having a third impurity concentration higher than the first impurity concentration formed outside and spaced from the gate electrode, wherein an n-type effective impurity concentration of an intermediate region between the gate electrode and the n+-type drain region is higher than an n-type effective impurity concentration of the overlap region.

摘要翻译： 半导体器件包括：p型有源区; 栅电极穿过有源区; 具有第一杂质浓度并由漏极侧区域形成到栅电极下方的区域的n型LDD区域; 具有第二杂质浓度的p型沟道区，由源极侧区域形成在栅极电极下方的区域，与栅极电极下方的LDD区域形成重叠区域，沟道区域比LDD区域浅; 形成在栅电极外的n型源区; 以及n +型漏极区，其具有比形成在所述栅电极外部并与所述栅电极间隔开的第一杂质浓度高的第三杂质浓度，其中所述栅电极和所述n +型漏极区之间的中间区域的n型有效杂质浓度 高于重叠区域的n型有效杂质浓度。

公开(公告)号：US08362522B2

公开(公告)日：2013-01-29

申请号：US13241298

申请日：2011-09-23

申请人： Masashi Shima

发明人： Masashi Shima

IPC分类号： H01L31/00

CPC分类号： H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： In a semiconductor film having a heterojunction structure, for example a semiconductor film including a SiGe layer and a Si layer formed on the SiGe layer, impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer becomes higher than that in the upper, Si layer by exploiting the fact that there is a difference between the SiGe layer and the Si layer in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film 11 is of the conductivity type opposite to that of the transistor (p-type in the case of an n-type MOS transistor whereas n-type in the case of a p-type MOS transistor). In this way, the mobility in a semiconductor device including a semiconductor film having a heterojunction structure with a compression strain structure is increased, thereby improving the transistor characteristics and reliability of the device.

摘要翻译： 在具有异质结结构的半导体膜中，例如包含形成在SiGe层上的SiGe层和Si层的半导体膜，以下层SiGe层中的杂质浓度变得高于 通过利用SiGe层和Si层之间在杂质的扩散系数中存在差异的事实，在上层Si层中。 包含在半导体膜11中的杂质的导电类型与晶体管的导电类型相反（在n型MOS晶体管的情况下为p型，而在p型MOS晶体管的情况下为n型）。 以这种方式，包括具有具有压缩应变结构的异质结结构的半导体膜的半导体器件中的迁移率增加，从而提高器件的晶体管特性和可靠性。

公开(公告)号：US20120149188A1

公开(公告)日：2012-06-14

申请号：US13397885

申请日：2012-02-16

申请人： Masashi Shima

发明人： Masashi Shima

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

摘要： The semiconductor device includes an n-channel transistor including n-type source/drain regions and a first gate electrode, a first sidewall insulating film formed on a side wall of the first gate electrode and having a Young's modulus smaller than a Young's modulus of silicon, a p-channel transistor including p-type source/drain regions and a second gate electrode, a second sidewall insulating film formed on a side wall of the second gate electrode and having a Young's modulus larger than the Young's modulus of silicon, a tensile stressor film formed, covering the n-channel transistor, and a compressive stressor film formed, covering the p-channel transistor.

摘要翻译： 该半导体器件包括n沟道晶体管，其包括n型源极/漏极区域和第一栅极电极，第一侧壁绝缘膜形成在第一栅电极的侧壁上并且具有小于杨氏模量的杨氏模量 ，包括p型源极/漏极区域和第二栅极电极的p沟道晶体管，形成在第二栅电极的侧壁上并具有大于杨氏杨氏模量的杨氏模量的第二侧壁绝缘膜， 形成的应力膜，覆盖n沟道晶体管，形成压应力膜，覆盖p沟道晶体管。

公开(公告)号：US20100240177A1

公开(公告)日：2010-09-23

申请号：US12704745

申请日：2010-02-12

申请人： Masashi Shima

发明人： Masashi Shima

IPC分类号： H01L21/8238

CPC分类号： H01L27/088 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device includes, forming an isolation region defining a first region and a second region, injecting a first impurity of a first conductivity type into the first region and the second region, forming a first gate insulating film and a first gate electrode over the first region, forming a second gate insulating film and a second gate electrode over the second region, forming a first mask layer over a first portion of the second region to expose a second portion of the second region and the first region, and injecting a second impurity of the first conductivity type into the semiconductor substrate from a direction diagonal to a surface of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法包括：形成限定第一区域和第二区域的隔离区域，将第一导电类型的第一杂质注入到第一区域和第二区域中，形成第一栅极绝缘膜和第一栅极 在第二区域上形成第二栅极绝缘膜和第二栅电极，在第二区域的第一部分上形成第一掩模层以暴露第二区域和第一区域的第二部分，以及 从与半导体衬底的表面对角的方向向半导体衬底注入第一导电类型的第二杂质。

公开(公告)号：US20100237445A1

公开(公告)日：2010-09-23

申请号：US12789697

申请日：2010-05-28

申请人： Masashi Shima

发明人： Masashi Shima

IPC分类号： H01L29/78

CPC分类号： H01L21/28052 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/7843 ,  H01L29/7845

摘要： To solve the problem, a MISFET covered with an insulating film which generates stress is provided. The MISFET including a gate insulating film; a gate electrode disposed on the gate insulating film, the gate electrode including a polysilicon portion and a silicide portion; and a source/drain disposed adjacent to the gate electrode, in which the ratio between the polysilicon portion and the silicide portion is determined depending on a strain for enhancing the driving capability of the MISFET, the strain being generated on the basis of the stress through the gate electrode in a channel region of the MISFET.

摘要翻译： 为了解决这个问题，提供了覆盖有产生应力的绝缘膜的MISFET。 MISFET包括栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极，所述栅电极包括多晶硅部分和硅化物部分; 以及与栅电极相邻设置的源极/漏极，其中根据用于增强MISFET的驱动能力的应变来确定多晶硅部分和硅化物部分之间的比率，该应变是基于通过 栅极电极在MISFET的沟道区域中。

公开(公告)号：US20100102365A1

公开(公告)日：2010-04-29

申请号：US12651606

申请日：2010-01-04

申请人： Masashi Shima

发明人： Masashi Shima

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

摘要： A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material. a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

摘要翻译： 半导体器件包括具有突起的硅衬底，形成在硅衬底的突起的上表面上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在硅衬底上的源极/漏极区域 所述第一侧壁形成在所述硅基板的所述突起的侧表面上，所述第一侧壁包含绝缘材料。 形成在所述第一侧壁上的第二侧壁，所述第二侧壁具有形成在所述硅基板的所述突起的上表面下方的底部，所述第二侧壁包含杨氏模量大于所述硅基板的杨氏模量的材料 以及形成在栅电极和第二侧壁上的应力膜。

公开(公告)号：US20090179278A1

公开(公告)日：2009-07-16

申请号：US12411016

申请日：2009-03-25

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/7843

摘要： In a p-type MOS transistor, a gate electrode is partially removed by a predetermined wet etching, so that an upper portion of the gate electrode is formed to be lower than an upper portion of a sidewall insulation film. As a result of such a constitution, in spite of formation of a tensile stress (TSEL) film leading to deterioration of characteristics of a p-type MOS transistor by nature, stresses applied from the TESL film to the gate electrode and the sidewall insulation film are dispersed as indicated by broken arrows in the drawing, and consequently, a compressive stress is applied to a channel region, so that a compressive strain is introduced. As stated above, in the p-type MOS transistor, in spite of formation of the TESL film, in reality, a strain to improve characteristics of the p-type MOS transistor is given to the channel region.

摘要翻译： 在p型MOS晶体管中，通过预定的湿蚀刻部分去除栅电极，使得栅电极的上部形成为低于侧壁绝缘膜的上部。 作为这种结构的结果，尽管形成导致p型MOS晶体管特性劣化的拉伸应力（TSEL）膜，但是从TESL膜施加到栅电极和侧壁绝缘膜的应力 如图中虚线箭头所示分散，因此，对通道区域施加压缩应力，从而引入压缩应变。 如上所述，在p型MOS晶体管中，尽管形成了TESL膜，但实际上，向沟道区域施加了提高p型MOS晶体管的特性的应变。

公开(公告)号：US20080277732A1

公开(公告)日：2008-11-13

申请号：US12176616

申请日：2008-07-21

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

摘要： A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions.

摘要翻译： P沟道MOS晶体管包括通过栅极绝缘膜形成在硅衬底上的栅电极，形成在硅衬底内的栅电极下方的沟道区，以及形成在p型沟道MOS晶体管上的p型源极区和p型漏极区 硅衬底内的沟道区的相对侧。 在p沟道MOS晶体管中，第一和第二侧壁绝缘膜布置在栅电极的相对的侧壁面上。 第一和第二p型外延区分别形成在硅衬底上的第一和第二侧壁绝缘膜的外侧，并且第一和第二p型外延区被布置成高于栅电极。 存储拉伸应力并经由第一和第二侧壁绝缘膜覆盖栅电极的应力膜连续地布置在第一和第二p型外延区上。

公开(公告)号：US20070063222A1

公开(公告)日：2007-03-22

申请号：US11520766

申请日：2006-09-14

申请人： Masashi Shima

发明人： Masashi Shima

IPC分类号： H01L31/00

CPC分类号： H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： In a semiconductor film having a heterojunction structure, for example a semiconductor film (11) including a SiGe layer (2) and a Si layer (3) formed on the SiGe layer (2), impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer (2) becomes higher than that in the upper, Si layer (3) by exploiting the fact that there is a difference between the SiGe layer (2) and the Si layer (3) in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film 11 is of the conductivity type opposite to that of the transistor (p-type in the case of an n-type MOS transistor whereas n-type in the case of a p-type MOS transistor). In this way, the mobility in a semiconductor device including a semiconductor film having a heterojunction structure with a compression strain structure is increased, thereby improving the transistor characteristics and reliability of the device.

摘要翻译： 在具有异质结结构的半导体膜中，例如在SiGe层（2）上形成有SiGe层（2）和Si层（3）的半导体膜（11），杂质浓度被控制为 SiGe层（2）中的SiGe层（2）和Si层（3）之间的差异在下层SiGe层（2）中的杂质浓度变得高于上层Si层（3） 杂质扩散系数。 包含在半导体膜11中的杂质的导电类型与晶体管的导电类型相反（在n型MOS晶体管的情况下是p型，而在p型MOS晶体管的情况下是n型）。 以这种方式，包括具有具有压缩应变结构的异质结结构的半导体膜的半导体器件中的迁移率增加，从而提高器件的晶体管特性和可靠性。