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1.发明申请公开(公告)号：US20120262318A1
公开(公告)日：2012-10-18
申请号：US13443297
申请日：2012-04-10
IPC分类号： H03M1/10
CPC分类号： H03M1/1057 , H03M1/1215
摘要： Various embodiments allow for background calibration of channel-to-channel mismatch errors.In certain embodiments calibration is accomplished by comparing the output of I-ADCs against the output of a reference ADC and correlating the difference to a known function to obtain a correction signal that can be used to correct channel-to-channel mismatch errors.
摘要翻译： 各种实施例允许对信道到信道不匹配错误的背景校准。 在某些实施例中，通过将I-ADC的输出与参考ADC的输出进行比较来实现校准，并将该差与已知功能相关，以获得可用于校正信道到信道失配错误的校正信号。
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2.发明授权公开(公告)号：US08519875B2
公开(公告)日：2013-08-27
申请号：US13443297
申请日：2012-04-10
IPC分类号： H03M1/10
CPC分类号： H03M1/1057 , H03M1/1215
摘要： Various embodiments allow for background calibration of channel-to-channel mismatch errors. In certain embodiments calibration is accomplished by comparing the output of I-ADCs against the output of a reference ADC and correlating the difference to a known function to obtain a correction signal that can be used to correct channel-to-channel mismatch errors.
摘要翻译： 各种实施例允许对信道到信道不匹配错误的背景校准。 在某些实施例中，通过将I-ADC的输出与参考ADC的输出进行比较来实现校准，并将该差与已知功能相关，以获得可用于校正信道到信道失配错误的校正信号。
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3.发明申请NONLINEAR AND CONCURRENT DIGITAL CONTROL FOR A HIGHLY DIGITAL PHASE-LOCKED LOOP 有权用于高数字相位锁定环的非线性和并流数字控制公开(公告)号：US20120218013A1
公开(公告)日：2012-08-30
申请号：US13219065
申请日：2011-08-26
IPC分类号： H03L7/08
CPC分类号： H03L7/093 , H03L7/1075
摘要： A phase-locked loop circuitry includes an oscillator circuitry having an input and an output. A phase detector circuit is connected to the output of the oscillator circuitry and has outputs thereof. A digital loop filter circuit is connected to the outputs of the phase detector circuitry and has outputs thereof. The outputs of the digital loop filter circuit are coupled, through a summing circuit, to the input of the oscillator circuitry. Values associated with the outputs of the digital loop filter circuit are updated concurrently based upon values associated with the outputs of the phase detector circuitry. One output of the digital loop filter circuitry has a high-pass transfer function.
摘要翻译： 锁相环电路包括具有输入和输出的振荡器电路。 相位检测器电路连接到振荡器电路的输出并具有其输出。 数字环路滤波器电路连接到相位检测器电路的输出并具有其输出。 数字环路滤波器电路的输出通过求和电路耦合到振荡器电路的输入端。 与数字环路滤波器电路的输出相关联的值基于与相位检测器电路的输出相关联的值同时更新。 数字环路滤波器电路的一个输出具有高通传递功能。
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4.发明授权Nonlinear and concurrent digital control for a highly digital phase-locked loop 有权用于高数字锁相环的非线性和并发数字控制公开(公告)号：US08432197B2
公开(公告)日：2013-04-30
申请号：US13219065
申请日：2011-08-26
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/1075
摘要： A phase-locked loop circuitry includes an oscillator circuitry having an input and an output. A phase detector circuit is connected to the output of the oscillator circuitry and has outputs thereof. A digital loop filter circuit is connected to the outputs of the phase detector circuitry and has outputs thereof. The outputs of the digital loop filter circuit are coupled, through a summing circuit, to the input of the oscillator circuitry. Values associated with the outputs of the digital loop filter circuit are updated concurrently based upon values associated with the outputs of the phase detector circuitry. One output of the digital loop filter circuitry has a high-pass transfer function.
摘要翻译： 锁相环电路包括具有输入和输出的振荡器电路。 相位检测器电路连接到振荡器电路的输出并具有其输出。 数字环路滤波器电路连接到相位检测器电路的输出并具有其输出。 数字环路滤波器电路的输出通过求和电路耦合到振荡器电路的输入端。 与数字环路滤波器电路的输出相关联的值基于与相位检测器电路的输出相关联的值同时更新。 数字环路滤波器电路的一个输出具有高通传递功能。
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