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公开(公告)号：US20140241077A1
公开(公告)日：2014-08-28
申请号：US13781159
申请日：2013-02-28
申请人： Atul KATOCH , Mayank TAYAL
发明人： Atul KATOCH , Mayank TAYAL
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/227 , G11C11/41 , G11C11/417 , G11C29/50012
摘要： A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.
摘要翻译： 确定流过跟踪电路的列中的电压线和/或数据线的电流。 确定跟踪电路的阈值跟踪时间延迟。 基于由电压线和/或数据线处理的确定的电流和确定的阈值跟踪时间延迟，跟踪电路中的多个列，多个列的每列中的多个第一单元，以及数字 确定多个列的每列中的第二单元格。
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公开(公告)号：US09324412B2
公开(公告)日：2016-04-26
申请号：US13791025
申请日：2013-03-08
申请人： Atul Katoch , Mayank Tayal
发明人： Atul Katoch , Mayank Tayal
IPC分类号： G11C7/22 , G11C11/419 , G11C7/08 , G11C7/12
CPC分类号： G11C11/419 , G11C7/08 , G11C7/12
摘要： A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit.
摘要翻译： 存储电路包括存储单元和数据电路。 在存储单元的写入操作中，数据电路被配置为向数据电路的第一输出提供第一写入逻辑值，并向数据电路的第二输出提供第二写入逻辑值。 第一个写入逻辑值与第二个写入逻辑值不同。 在存储单元的读取操作中，数据电路被配置为向数据电路的第一输出和第二输出提供相同的逻辑值。
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公开(公告)号：US08929160B2
公开(公告)日：2015-01-06
申请号：US13781159
申请日：2013-02-28
申请人： Atul Katoch , Mayank Tayal
发明人： Atul Katoch , Mayank Tayal
CPC分类号： G11C7/12 , G11C7/227 , G11C11/41 , G11C11/417 , G11C29/50012
摘要： A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.
摘要翻译： 确定流过跟踪电路的列中的电压线和/或数据线的电流。 确定跟踪电路的阈值跟踪时间延迟。 基于由电压线和/或数据线处理的确定的电流和确定的阈值跟踪时间延迟，跟踪电路中的多个列，多个列的每列中的多个第一单元，以及数字 确定多个列的每列中的第二单元格。
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公开(公告)号：US20130010561A1
公开(公告)日：2013-01-10
申请号：US13618646
申请日：2012-09-14
申请人： Atul KATOCH , Mayank TAYAL
发明人： Atul KATOCH , Mayank TAYAL
摘要： Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.
摘要翻译： 本发明的实施例涉及读出放大器。 在涉及与存储器单元一起使用的读出放大器的实施例中，使用均衡信号将信号BL，ZBL，SN和SP预充电并均衡到电压参考值，例如Vref。 施加补偿信号，例如SAC，以补偿读出放大器中的晶体管之间的失配。 字线WL被激活以将存储器单元连接到位线，例如位线ZBL。 由于存储单元与所连接的位线ZBL共享电荷，所以在位线BL和ZBL之间产生差分信号。 当位线BL和ZBL之间的足够的分割被开发时，信号SP和SAE升高到VDD（当信号SN已经降低到VSS时），以使得读出放大器接通，并使其能够按需要起作用。 还公开了其它实施例和示例性应用。
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公开(公告)号：US20100246303A1
公开(公告)日：2010-09-30
申请号：US12731625
申请日：2010-03-25
申请人： Atul KATOCH , Mayank TAYAL
发明人： Atul KATOCH , Mayank TAYAL
IPC分类号： G11C7/06
摘要： Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.
摘要翻译： 本发明的实施例涉及读出放大器。 在涉及与存储器单元一起使用的读出放大器的实施例中，使用均衡信号将信号BL，ZBL，SN和SP预充电并均衡到电压参考值，例如Vref。 施加补偿信号，例如SAC，以补偿读出放大器中的晶体管之间的失配。 字线WL被激活以将存储器单元连接到位线，例如位线ZBL。 由于存储单元与所连接的位线ZBL共享电荷，所以在位线BL和ZBL之间产生差分信号。 当位线BL和ZBL之间的足够的分割被开发时，信号SP和SAE升高到VDD（当信号SN已经降低到VSS时），以使得读出放大器接通，并使其能够按需要起作用。 还公开了其它实施例和示例性应用。
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公开(公告)号：US08605529B2
公开(公告)日：2013-12-10
申请号：US13618646
申请日：2012-09-14
申请人： Atul Katoch , Mayank Tayal
发明人： Atul Katoch , Mayank Tayal
IPC分类号： G11C7/02
摘要： Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.
摘要翻译： 本发明的实施例涉及读出放大器。 在涉及与存储器单元一起使用的读出放大器的实施例中，使用均衡信号将信号BL，ZBL，SN和SP预充电并均衡到电压参考值，例如Vref。 施加补偿信号，例如SAC，以补偿读出放大器中的晶体管之间的失配。 字线WL被激活以将存储器单元连接到位线，例如位线ZBL。 由于存储单元与所连接的位线ZBL共享电荷，所以在位线BL和ZBL之间产生差分信号。 当位线BL和ZBL之间的足够的分割被开发时，信号SP和SAE升高到VDD（当信号SN已经降低到VSS时），以使得读出放大器接通，并使其能够按需要起作用。 还公开了其它实施例和示例性应用。
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公开(公告)号：US08295112B2
公开(公告)日：2012-10-23
申请号：US12731625
申请日：2010-03-25
申请人： Atul Katoch , Mayank Tayal
发明人： Atul Katoch , Mayank Tayal
IPC分类号： G11C7/02
摘要： Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.
摘要翻译： 本发明的实施例涉及读出放大器。 在涉及与存储器单元一起使用的读出放大器的实施例中，使用均衡信号将信号BL，ZBL，SN和SP预充电并均衡到电压参考值，例如Vref。 施加补偿信号，例如SAC，以补偿读出放大器中的晶体管之间的失配。 字线WL被激活以将存储器单元连接到位线，例如位线ZBL。 由于存储单元与所连接的位线ZBL共享电荷，所以在位线BL和ZBL之间产生差分信号。 当位线BL和ZBL之间的足够的分割被开发时，信号SP和SAE升高到VDD（当信号SN已经降低到VSS时），以使得读出放大器接通，并使其能够按需要起作用。 还公开了其它实施例和示例性应用。
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