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公开(公告)号：US08581658B2
公开(公告)日：2013-11-12
申请号：US13082918
申请日：2011-04-08
摘要： A charge pump circuit comprises a first node, a second node, and at least one capacitance stage coupled between the first node and the second node. Capacitance stages of the at least one capacitance stage are coupled in series. A capacitance stage of the at least one capacitance stage includes a capacitive device and a voltage limiter coupled in parallel with the capacitor. The voltage limiter is configured to limit a voltage dropped across the capacitor. The capacitive device and the voltage limiter are configured such that a first current flowing through a first branch having the voltage limiter is more than a second current flowing through a second branch having the capacitive device.
摘要翻译： 电荷泵电路包括第一节点，第二节点和耦合在第一节点和第二节点之间的至少一个电容级。 至少一个电容级的电容级串联耦合。 至少一个电容级的电容级包括电容器件和与电容器并联耦合的限压器。 电压限制器被配置为限制电容器下降的电压。 电容性器件和限压器被配置为使流过具有限压器的第一支路的第一电流大于流过具有电容器件的第二支路的第二电流。
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公开(公告)号：US20130223174A1
公开(公告)日：2013-08-29
申请号：US13403425
申请日：2012-02-23
申请人： Atul KATOCH
发明人： Atul KATOCH
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/417
摘要： A data split between a first data line and a second data line is caused to develop. At least one of the following sets of steps is performed: 1) a first power supply line of a sense amplifier is caused to rise towards a first power supply voltage value, and when the first power supply line reaches a first predetermined voltage value, the first power supply is caused to rise above the first power supply voltage value; and 2) a second power supply line of the sense amplifier is caused to fall towards a second power supply voltage value, and when the second power supply line reaches a second predetermined voltage value, the second power supply line is caused to fall below the second power supply voltage value.
摘要翻译： 导致在第一数据线和第二数据线之间分割的数据。 执行以下步骤集中的至少一个：1）使感测放大器的第一电源线朝向第一电源电压值上升，并且当第一电源线达到第一预定电压值时， 使第一电源上升到高于第一电源电压值; 以及2）使所述读出放大器的第二电源线落到第二电源电压值，并且当所述第二电源线达到第二预定电压值时，使所述第二电源线落在所述第二电源电压值以下 电源电压值。
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公开(公告)号：US20120039143A1
公开(公告)日：2012-02-16
申请号：US12855289
申请日：2010-08-12
申请人： Atul KATOCH
发明人： Atul KATOCH
IPC分类号： G11C7/06
CPC分类号： G11C11/4091
摘要： A circuit having a sensing circuit and at least one of a first node and a second node is described. The sensing circuit includes a pair of a first type transistors and a pair of a second type transistors. Each transistor of the pair of the first type transistors is coupled in series with a transistor of the pair of the second type transistors. The first node has a first voltage and is coupled to each bulk of each transistor of the pair of the first type transistors. The second node has a second voltage and is coupled to each bulk of each transistor of the pair of the second type transistors.
摘要翻译： 描述具有感测电路和第一节点和第二节点中的至少一个的电路。 感测电路包括一对第一类型晶体管和一对第二类型晶体管。 该对第一类型晶体管中的每个晶体管与该对第二类型晶体管的晶体管串联耦合。 第一节点具有第一电压并且耦合到该对第一类型晶体管的每个晶体管的每个主体。 第二节点具有第二电压并且耦合到该对第二类型晶体管的每个晶体管的每个主体。
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公开(公告)号：US20110069570A1
公开(公告)日：2011-03-24
申请号：US12767979
申请日：2010-04-27
申请人： Atul KATOCH
发明人： Atul KATOCH
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C11/4076 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes at least one first memory cell of a first memory array for storing a first datum. The at least one first memory cell is coupled with a first word line and a first bit line. A first bit line bar is disposed substantially parallel with the first bit line. A first switch is coupled between a sense amplifier and the first bit line bar. The first switch can electrically isolate the sense amplifier from the first bit line bar if the sense amplifier is capable of sensing a first voltage difference between the first bit line. The first bit line bar and the first voltage difference is substantially equal to or larger than a predetermined value.
摘要翻译： 存储器电路包括用于存储第一数据的第一存储器阵列的至少一个第一存储单元。 所述至少一个第一存储单元与第一字线和第一位线耦合。 第一位线条与第一位线基本平行地设置。 第一开关耦合在读出放大器和第一位线条之间。 如果读出放大器能够检测第一位线之间的第一电压差，则第一开关可以将读出放大器与第一位线条电隔离。 第一位线条和第一电压差基本上等于或大于预定值。
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公开(公告)号：US07429885B2
公开(公告)日：2008-09-30
申请号：US10556113
申请日：2004-08-07
CPC分类号： H03K19/00346 , H03K5/08 , H04L25/085
摘要： A clamper circuit for receiving an input signal from a victim wire, the clamper circuit being capable of receiving aggressor signals from aggressor wires, the aggressor wires being the signal wires that can potentially induce crosstalk on the victim wire and an output signal being selectively enabled based on the logic states of the input signal and the aggressor signals, the clamper circuit also being capable of accelerating the switching of the victim wire when an opposite transition occurs on the aggressors and victim wire at the same time, so as to thereby reduce worst case delay and improve the signal integrity.
摘要翻译： 用于从受害线接收输入信号的钳位电路，钳位电路能够接收来自侵扰线的侵扰信号，侵略线是潜在地在受害线上诱发串扰的信号线，以及基于有选择地启用的输出信号 在输入信号和侵略者信号的逻辑状态下，当在侵略者和受害线同时发生相反的转变时，钳位电路还能够加速受害线的切换，从而减少最坏情况 延迟和提高信号完整性。
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公开(公告)号：US20050257947A1
公开(公告)日：2005-11-24
申请号：US10519767
申请日：2003-06-17
IPC分类号： H01L21/82 , G06F17/50 , H01L27/02 , H01L27/118 , H03K19/177 , H01B7/00
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/118
摘要： An integrated circuit (300) has a regular grid formed by substantially identical building blocks (100a-i). To avoid possible routing conflicts around the edges of the integrated circuit (300), which can be introduced by the use of a single type of an asymmetric building block, the integrated circuit (300) is extended with routing cells (200) that provide routing at the edges of the grid that are uncovered by the routing networks of the building blocks (100a-i). The routing cells (200) and the switch cell (250) are combined with a first routing structure (330) and a second routing structure (340) to form a routing network (280) surrounding the grid of the integrated circuit (300). Consequently, an integrated circuit (300) is presented that comprises only a single type of building block (100a-i) but still has a fully symmetric routing architecture.
摘要翻译： 集成电路（300）具有由基本上相同的构建块（100a-i）形成的规则网格。 为了避免可以通过使用单一类型的非对称构建块引入的集成电路（300）的边缘周围的可能的路由冲突，集成电路（300）被扩展，路由单元（200）提供路由 在由所述构建块（100a）的路由网络未覆盖的所述网格的边缘处。 路由单元（200）和交换单元（250）与第一路由结构（330）和第二路由结构（340）组合以形成围绕集成电路（300）的网格的路由网络（280）。 因此，提出了仅包括单一类型的构建块（100a-i）但仍具有完全对称的路由架构的集成电路（300）。
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公开(公告)号：US08873321B2
公开(公告)日：2014-10-28
申请号：US13403425
申请日：2012-02-23
申请人： Atul Katoch
发明人： Atul Katoch
IPC分类号： G11C7/02
CPC分类号： G11C5/147 , G11C11/417
摘要： A data split between a first data line and a second data line is caused to develop. At least one of the following sets of steps is performed: 1) a first power supply line of a sense amplifier is caused to rise towards a first power supply voltage value, and when the first power supply line reaches a first predetermined voltage value, the first power supply is caused to rise above the first power supply voltage value; and 2) a second power supply line of the sense amplifier is caused to fall towards a second power supply voltage value, and when the second power supply line reaches a second predetermined voltage value, the second power supply line is caused to fall below the second power supply voltage value.
摘要翻译： 导致在第一数据线和第二数据线之间分割的数据。 执行以下步骤集中的至少一个：1）使感测放大器的第一电源线朝向第一电源电压值上升，并且当第一电源线达到第一预定电压值时， 使第一电源上升到高于第一电源电压值; 以及2）使所述读出放大器的第二电源线落到第二电源电压值，并且当所述第二电源线达到第二预定电压值时，使所述第二电源线落在所述第二电源电压值以下 电源电压值。
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公开(公告)号：US20120256681A1
公开(公告)日：2012-10-11
申请号：US13082918
申请日：2011-04-08
IPC分类号： G05F3/02
摘要： A charge pump circuit comprises a first node, a second node, and at least one capacitance stage coupled between the first node and the second node. Capacitance stages of the at least one capacitance stage are coupled in series. A capacitance stage of the at least one capacitance stage includes a capacitive device and a voltage limiter coupled in parallel with the capacitor. The voltage limiter is configured to limit a voltage dropped across the capacitor. The capacitive device and the voltage limiter are configured such that a first current flowing through a first branch having the voltage limiter is more than a second current flowing through a second branch having the capacitive device.
摘要翻译： 电荷泵电路包括第一节点，第二节点和耦合在第一节点和第二节点之间的至少一个电容级。 至少一个电容级的电容级串联耦合。 至少一个电容级的电容级包括电容器件和与电容器并联耦合的限压器。 电压限制器被配置为限制电容器下降的电压。 电容性器件和限压器被配置为使流过具有限压器的第一支路的第一电流大于流过具有电容器件的第二支路的第二电流。
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公开(公告)号：US20120032511A1
公开(公告)日：2012-02-09
申请号：US12852638
申请日：2010-08-09
IPC分类号： H02J1/00
CPC分类号： G11C11/4091 , Y10T307/50
摘要： Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.
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10.发明授权公开(公告)号：US07616051B2
公开(公告)日：2009-11-10
申请号：US11911881
申请日：2006-04-20
CPC分类号： H03K19/0019
摘要： An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101, 102) from an active mode to a standby mode. The IC (10) comprises a further switch (141) having a first terminal coupled to a node (121) of the first conductive path between the first switch (131) and the first functional block (101) and a second terminal coupled to a node (122) of the second conductive path between the second switch (132) and the second functional block (102). The further switch (141) has a control terminal responsive to an enable signal indicating that the first switch (131) and the second switch (132) are disabled, thus allowing the recycling of charge between the first functional block (101) and the second functional block (102).
摘要翻译： 集成电路（10）包括多个功能块（101,102,103），每个功能块（101,102,103）被耦合在第一电源线（110）和第二电源线（ 120）。 第一功能块（101）经由包括第一开关（131）的第一导电路径耦合到第一电源线（110），并且第二功能块（102）经由第一电源线（110）经由 包括第二开关（132）的第二导电路径，所述第一开关（131）和所述第二开关（132）被布置成分别将所述第一功能块（101）和所述第二功能块（102）与所述第一电源 线路（110），用于将所述功能块（101,102）从活动模式切换到待机模式。 IC（10）包括另外的开关（141），其具有耦合到第一开关（131）和第一功能块（101）之间的第一导电路径的节点（121）的第一端子和耦合到第一端子 在第二开关（132）和第二功能块（102）之间的第二导电路径的节点（122）。 另外的开关（141）具有响应于指示第一开关（131）和第二开关（132）被禁用的使能信号的控制端子，从而允许在第一功能块（101）和第二开关 功能块（102）。
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