公开(公告)号：US09324412B2

公开(公告)日：2016-04-26

申请号：US13791025

申请日：2013-03-08

申请人： Atul Katoch ,  Mayank Tayal

发明人： Atul Katoch ,  Mayank Tayal

IPC分类号： G11C7/22 ,  G11C11/419 ,  G11C7/08 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C7/08 ,  G11C7/12

摘要： A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit.

摘要翻译： 存储电路包括存储单元和数据电路。 在存储单元的写入操作中，数据电路被配置为向数据电路的第一输出提供第一写入逻辑值，并向数据电路的第二输出提供第二写入逻辑值。 第一个写入逻辑值与第二个写入逻辑值不同。 在存储单元的读取操作中，数据电路被配置为向数据电路的第一输出和第二输出提供相同的逻辑值。

公开(公告)号：US08929160B2

公开(公告)日：2015-01-06

申请号：US13781159

申请日：2013-02-28

申请人： Atul Katoch ,  Mayank Tayal

发明人： Atul Katoch ,  Mayank Tayal

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C7/12 ,  G11C7/227 ,  G11C11/41 ,  G11C11/417 ,  G11C29/50012

摘要： A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.

摘要翻译： 确定流过跟踪电路的列中的电压线和/或数据线的电流。 确定跟踪电路的阈值跟踪时间延迟。 基于由电压线和/或数据线处理的确定的电流和确定的阈值跟踪时间延迟，跟踪电路中的多个列，多个列的每列中的多个第一单元，以及数字 确定多个列的每列中的第二单元格。

公开(公告)号：US08605529B2

公开(公告)日：2013-12-10

申请号：US13618646

申请日：2012-09-14

申请人： Atul Katoch ,  Mayank Tayal

发明人： Atul Katoch ,  Mayank Tayal

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C7/08

摘要： Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.

摘要翻译： 本发明的实施例涉及读出放大器。 在涉及与存储器单元一起使用的读出放大器的实施例中，使用均衡信号将信号BL，ZBL，SN和SP预充电并均衡到电压参考值，例如Vref。 施加补偿信号，例如SAC，以补偿读出放大器中的晶体管之间的失配。 字线WL被激活以将存储器单元连接到位线，例如位线ZBL。 由于存储单元与所连接的位线ZBL共享电荷，所以在位线BL和ZBL之间产生差分信号。 当位线BL和ZBL之间的足够的分割被开发时，信号SP和SAE升高到VDD（当信号SN已经降低到VSS时），以使得读出放大器接通，并使其能够按需要起作用。 还公开了其它实施例和示例性应用。

公开(公告)号：US08295112B2

公开(公告)日：2012-10-23

申请号：US12731625

申请日：2010-03-25

申请人： Atul Katoch ,  Mayank Tayal

发明人： Atul Katoch ,  Mayank Tayal

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C7/08

摘要： Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.

摘要翻译： 本发明的实施例涉及读出放大器。 在涉及与存储器单元一起使用的读出放大器的实施例中，使用均衡信号将信号BL，ZBL，SN和SP预充电并均衡到电压参考值，例如Vref。 施加补偿信号，例如SAC，以补偿读出放大器中的晶体管之间的失配。 字线WL被激活以将存储器单元连接到位线，例如位线ZBL。 由于存储单元与所连接的位线ZBL共享电荷，所以在位线BL和ZBL之间产生差分信号。 当位线BL和ZBL之间的足够的分割被开发时，信号SP和SAE升高到VDD（当信号SN已经降低到VSS时），以使得读出放大器接通，并使其能够按需要起作用。 还公开了其它实施例和示例性应用。

公开(公告)号：US08581658B2

公开(公告)日：2013-11-12

申请号：US13082918

申请日：2011-04-08

申请人： Atul Katoch ,  Cormac Michael O'Connell

发明人： Atul Katoch ,  Cormac Michael O'Connell

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/07 ,  H02M1/32

摘要： A charge pump circuit comprises a first node, a second node, and at least one capacitance stage coupled between the first node and the second node. Capacitance stages of the at least one capacitance stage are coupled in series. A capacitance stage of the at least one capacitance stage includes a capacitive device and a voltage limiter coupled in parallel with the capacitor. The voltage limiter is configured to limit a voltage dropped across the capacitor. The capacitive device and the voltage limiter are configured such that a first current flowing through a first branch having the voltage limiter is more than a second current flowing through a second branch having the capacitive device.

摘要翻译： 电荷泵电路包括第一节点，第二节点和耦合在第一节点和第二节点之间的至少一个电容级。 至少一个电容级的电容级串联耦合。 至少一个电容级的电容级包括电容器件和与电容器并联耦合的限压器。 电压限制器被配置为限制电容器下降的电压。 电容性器件和限压器被配置为使流过具有限压器的第一支路的第一电流大于流过具有电容器件的第二支路的第二电流。

公开(公告)号：US07429885B2

公开(公告)日：2008-09-30

申请号：US10556113

申请日：2004-08-07

申请人： Atul Katoch ,  Rinze Ida Mechtildis Peter Meijer ,  Sanjeev Kimar Jain

发明人： Atul Katoch ,  Rinze Ida Mechtildis Peter Meijer ,  Sanjeev Kimar Jain

IPC分类号： H03K5/08 ,  H03L5/00

CPC分类号： H03K19/00346 ,  H03K5/08 ,  H04L25/085

摘要： A clamper circuit for receiving an input signal from a victim wire, the clamper circuit being capable of receiving aggressor signals from aggressor wires, the aggressor wires being the signal wires that can potentially induce crosstalk on the victim wire and an output signal being selectively enabled based on the logic states of the input signal and the aggressor signals, the clamper circuit also being capable of accelerating the switching of the victim wire when an opposite transition occurs on the aggressors and victim wire at the same time, so as to thereby reduce worst case delay and improve the signal integrity.

摘要翻译： 用于从受害线接收输入信号的钳位电路，钳位电路能够接收来自侵扰线的侵扰信号，侵略线是潜在地在受害线上诱发串扰的信号线，以及基于有选择地启用的输出信号 在输入信号和侵略者信号的逻辑状态下，当在侵略者和受害线同时发生相反的转变时，钳位电路还能够加速受害线的切换，从而减少最坏情况 延迟和提高信号完整性。

公开(公告)号：US20050257947A1

公开(公告)日：2005-11-24

申请号：US10519767

申请日：2003-06-17

申请人： Katarzyna Leijten-Nowak ,  Atul Katoch

发明人： Katarzyna Leijten-Nowak ,  Atul Katoch

IPC分类号： H01L21/82 ,  G06F17/50 ,  H01L27/02 ,  H01L27/118 ,  H03K19/177 ,  H01B7/00

CPC分类号： G06F17/5068 ,  H01L27/0207 ,  H01L27/118

摘要： An integrated circuit (300) has a regular grid formed by substantially identical building blocks (100a-i). To avoid possible routing conflicts around the edges of the integrated circuit (300), which can be introduced by the use of a single type of an asymmetric building block, the integrated circuit (300) is extended with routing cells (200) that provide routing at the edges of the grid that are uncovered by the routing networks of the building blocks (100a-i). The routing cells (200) and the switch cell (250) are combined with a first routing structure (330) and a second routing structure (340) to form a routing network (280) surrounding the grid of the integrated circuit (300). Consequently, an integrated circuit (300) is presented that comprises only a single type of building block (100a-i) but still has a fully symmetric routing architecture.

摘要翻译： 集成电路（300）具有由基本上相同的构建块（100a-i）形成的规则网格。 为了避免可以通过使用单一类型的非对称构建块引入的集成电路（300）的边缘周围的可能的路由冲突，集成电路（300）被扩展，路由单元（200）提供路由 在由所述构建块（100a）的路由网络未覆盖的所述网格的边缘处。 路由单元（200）和交换单元（250）与第一路由结构（330）和第二路由结构（340）组合以形成围绕集成电路（300）的网格的路由网络（280）。 因此，提出了仅包括单一类型的构建块（100a-i）但仍具有完全对称的路由架构的集成电路（300）。

公开(公告)号：US08681576B2

公开(公告)日：2014-03-25

申请号：US13118956

申请日：2011-05-31

申请人： Atul Katoch ,  Arun Achyuthan ,  Cormac Michael O'Connell

发明人： Atul Katoch ,  Arun Achyuthan ,  Cormac Michael O'Connell

IPC分类号： G11C7/00

CPC分类号： G11C11/4094

摘要： A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a pair of data lines. The control signal line is configured to control the pre-charge and equalization devices. The word line is configured to electrically couple a memory cell to a data line of the pair of data lines. A first voltage value provided to the control signal line is from a first voltage source different from a second voltage source that generates a second voltage value for the word line.

摘要翻译： 电路包括一组预充电和均衡装置，控制信号线和字线。 该组预充电和均衡装置被配置为对一对数据线进行预充电和均衡。 控制信号线被配置为控制预充电和均衡装置。 字线被配置为将存储器单元电耦合到该对数据线的数据线。 提供给控制信号线的第一电压值来自不同于产生字线的第二电压值的第二电压源的第一电压源。

公开(公告)号：US07605740B2

公开(公告)日：2009-10-20

申请号：US12097040

申请日：2006-12-08

申请人： Marcel Pelgrom ,  Atul Katoch ,  Maarten Vertregt

发明人： Marcel Pelgrom ,  Atul Katoch ,  Maarten Vertregt

IPC分类号： H03M1/36

CPC分类号： H03M1/0673 ,  H03M1/365

摘要： A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.

摘要翻译： 闪存模数转换器包括由参考电压源供电的电阻串，用于提供一组等距参考电压，以及一组比较器，用于将模拟输入信号与参考电压进行比较。 一组开关被布置和控制以执行用于减轻组件之间的错配的影响的算法。 开关布置在参考电压源和电阻串之间，从而避免了比较器的参考输入中的开关。 电阻串优选为圆形。 转换器可以处理差分信号。

公开(公告)号：US20060244481A1

公开(公告)日：2006-11-02

申请号：US10558145

申请日：2004-05-17

申请人： Atul Katoch ,  Manish Garg ,  Evert Seevinck ,  Hendricus Veendrick

发明人： Atul Katoch ,  Manish Garg ,  Evert Seevinck ,  Hendricus Veendrick

IPC分类号： H03K19/003

CPC分类号： G06F13/4072

摘要： As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

摘要翻译： 随着技术的发展，片上互连变得越来越窄，这种互连的高度并没有随宽度而线性缩放。 这导致与相邻导线的耦合电容的增加，导致更高的串扰。 由于在接收线路时RC响应差，导致性能差，甚至可能导致非常嘈杂的环境中的故障​​。 提出了一种自适应阈值方案，其中接收机切换阈值根据总线线路中检测到的噪声进行调整。 这些噪声水平取决于前端处理（晶体管性能）以及后端处理（金属电阻，电容，宽度和间距）。 因此，电路自动补偿过程变化。