Abstract:
Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.
Abstract:
At least one pattern of a photomask is identified that has a likelihood of causing collapse of a microelectronic device feature that is formed using the photomask, due to surface tension of a solution that is applied to the feature during manufacture of the microelectronic device. The patterns of the photomask are then modified to reduce the likelihood of the collapse. The photomask may be formed and the photomask may be used to manufacture microelectronic devices. Related methods, systems, devices and computer program products are described.
Abstract:
At least one pattern of a photomask is identified that has a likelihood of causing collapse of a microelectronic device feature that is formed using the photomask, due to surface tension of a solution that is applied to the feature during manufacture of the microelectronic device. The patterns of the photomask are then modified to reduce the likelihood of the collapse. The photomask may be formed and the photomask may be used to manufacture microelectronic devices. Related methods, systems, devices and computer program products are described.
Abstract:
Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.
Abstract:
Asiatic acid derivatives having a modified A-ring, as represented by formula 1 are disclosed. ##STR1## Pharmaceutical compositions and methods of treating cancer and hepatotoxicity utilizing compounds of formula 1 are also disclosed.
Abstract:
Disclosed herein is a composition for plasma electrolytic oxidation (PEO) treatment of magnesium alloy products, which contains a sodium hydroxide (NaOH) solution as a main component, the composition comprising, based on the weight of sodium hydroxide contained in the sodium hydroxide solution: 1-20 wt % of sodium fluoride (NaF); 1-15 wt % of trisodium phosphate (Na3PO4); 1-10 wt % of sodium pyrophosphate (Na4P2O7); 1-20 wt % of aluminum hydroxide (Al(OH)3); 1-20 wt % of sodium fluorosilicate (Na2SiF6); 1-10 wt % of potassium hydroxide (KOH); 1-15 wt % of potassium acetate (C2H3O2K); and 1-10 wt % of rare earth metal powder. The disclosed composition can form a firm, dense and uniform oxide film on the surface of a magnesium alloy product.
Abstract:
Disclosed herein is a composition for plasma electrolytic oxidation (PEO) treatment of magnesium alloy products, which contains a sodium hydroxide (NaOH) solution as a main component, the composition comprising, based on the weight of sodium hydroxide contained in the sodium hydroxide solution: 1-20 wt % of sodium fluoride (NaF); 1-15 wt % of trisodium phosphate (Na3PO4); 1-10 wt % of sodium pyrophosphate (Na4P2O7); 1-20 wt % of aluminum hydroxide (Al(OH)3); 1-20 wt % of sodium fluorosilicate (Na2SiF6); 1-10 wt % of potassium hydroxide (KOH); 1-15 wt % of potassium acetate (C2H3O2K); and 1-10 wt % of rare earth metal powder. The disclosed composition can form a firm, dense and uniform oxide film on the surface of a magnesium alloy product.