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公开(公告)号：US08214602B2
公开(公告)日：2012-07-03
申请号：US12143985
申请日：2008-06-23
IPC分类号： G06F12/00
CPC分类号： G06F9/3842 , G06F9/3834 , G06F12/0831
摘要： In one embodiment, a processor comprises a data cache and a load/store unit (LSU). The LSU comprises a queue and a control unit, and each entry in the queue is assigned to a different load that has accessed the data cache but has not retired. The control unit is configured to update the data cache hit status of each load represented in the queue as a content of the data cache changes. The control unit is configured to detect a snoop hit on a first load in a first entry of the queue responsive to: the snoop index matching a load index stored in the first entry, the data cache hit status of the first load indicating hit, the data cache detecting a snoop hit for the snoop operation, and a load way stored in the first entry matching a first way of the data cache in which the snoop operation is a hit.
摘要翻译： 在一个实施例中，处理器包括数据高速缓存和加载/存储单元（LSU）。 LSU包括队列和控制单元，队列中的每个条目被分配给已访问数据高速缓存但尚未退出的不同负载。 控制单元被配置为随着数据高速缓存的内容改变而更新队列中表示的每个负载的数据高速缓存命中状态。 所述控制单元被配置为响应于：所述窥探索引匹配存储在所述第一条目中的加载索引，所述第一加载指示命中的数据高速缓存命中状态，所述第一加载指示命中的数据高速缓存命中状态， 数据高速缓存检测用于窥探操作的窥探命中，以及存储在第一条目中的加载方式，其与窥探操作是命中的数据高速缓存的第一路径相匹配。
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2.发明授权公开(公告)号：US07861066B2
公开(公告)日：2010-12-28
申请号：US11780684
申请日：2007-07-20
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3838 , G06F9/3844
摘要： A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued. In addition, a prediction unit within the processor may predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay. The processor also includes a decode unit that may decode instructions and in response to detecting the indication, may flag the given instruction operation. The scheduler may further inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.
摘要翻译： 用于抑制指令重放的机构包括具有一个或多个执行单元的处理器和发出由一个或多个执行单元执行的指令操作的调度器。 调度器还可以导致被确定为不正确执行以重播或重新发行的指令操作。 此外，处理器内的预测单元可以预测给定指令操作是否将重放，并提供给定指令操作将重放的指示。 处理器还包括解码单元，其可以解码指令并且响应于检测到指示，可以标记给定的指令操作。 调度器可以进一步禁止标记指令操作的发生，直到与被标记的指令相关联的状态良好。
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公开(公告)号：US20090319727A1
公开(公告)日：2009-12-24
申请号：US12143985
申请日：2008-06-23
IPC分类号： G06F12/08
CPC分类号： G06F9/3842 , G06F9/3834 , G06F12/0831
摘要： In one embodiment, a processor comprises a data cache and a load/store unit (LSU). The LSU comprises a queue and a control unit, and each entry in the queue is assigned to a different load that has accessed the data cache but has not retired. The control unit is configured to update the data cache hit status of each load represented in the queue as a content of the data cache changes. The control unit is configured to detect a snoop hit on a first load in a first entry of the queue responsive to: the snoop index matching a load index stored in the first entry, the data cache hit status of the first load indicating hit, the data cache detecting a snoop hit for the snoop operation, and a load way stored in the first entry matching a first way of the data cache in which the snoop operation is a hit.
摘要翻译： 在一个实施例中，处理器包括数据高速缓存和加载/存储单元（LSU）。 LSU包括队列和控制单元，队列中的每个条目被分配给已访问数据高速缓存但尚未退出的不同负载。 控制单元被配置为随着数据高速缓存的内容改变而更新队列中表示的每个负载的数据高速缓存命中状态。 所述控制单元被配置为响应于：所述窥探索引匹配存储在所述第一条目中的加载索引，所述第一加载指示命中的数据高速缓存命中状态，所述第一加载指示命中的数据高速缓存命中状态， 数据高速缓存检测用于窥探操作的窥探命中，以及存储在第一条目中的加载方式，其与窥探操作是命中的数据高速缓存的第一路径相匹配。
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公开(公告)号：US20090183035A1
公开(公告)日：2009-07-16
申请号：US11972166
申请日：2008-01-10
申请人： Michael G. Butler , Nhon Quach
发明人： Michael G. Butler , Nhon Quach
CPC分类号： G06F11/1497 , G06F11/1405 , G06F11/1641 , G06F11/1645
摘要： A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units and may consecutively dispatch a same floating-point instruction stream to a floating-point unit. The integer execution units may operate in lock-step such that during each clock cycle, each respective integer execution unit executes the same integer instruction. The floating-point unit may execute the same floating-point instruction stream twice. Prior to the integer instructions retiring, compare logic may detect a mismatch between execution results from each of the integer execution units. In addition, prior to the results of the floating-point instruction stream transferring out of the floating-point unit, the compare logic may also detect a mismatch between results of execution of each consecutive floating-point instruction stream. Further, in response to detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.
摘要翻译： 处理器核心包括指令解码单元，其可以向多个整数执行单元分派相同的整数指令流，并且可以将相同的浮点指令流连续地分派到浮点单元。 整数执行单元可以锁定步骤操作，使得在每个时钟周期期间，每个相应的整数执行单元执行相同的整数指令。 浮点单元可以执行相同的浮点指令流两次。 在整数指令退出之前，比较逻辑可以检测来自每个整数执行单元的执行结果之间的不匹配。 此外，在浮点指令流从浮点单元传出的结果之前，比较逻辑还可以检测每个连续浮点指令流的执行结果之间的不匹配。 此外，响应于检测到任何不匹配，比较逻辑可能导致导致不匹配的指令被重新执行。
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公开(公告)号：US20090024838A1
公开(公告)日：2009-01-22
申请号：US11780684
申请日：2007-07-20
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3838 , G06F9/3844
摘要： A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued. In addition, a prediction unit within the processor may predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay. The processor also includes a decode unit that may decode instructions and in response to detecting the indication, may flag the given instruction operation. The scheduler may further inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.
摘要翻译： 用于抑制指令重放的机构包括具有一个或多个执行单元的处理器和发出由一个或多个执行单元执行的指令操作的调度器。 调度器还可以导致被确定为不正确执行以重播或重新发行的指令操作。 此外，处理器内的预测单元可以预测给定指令操作是否将重放，并提供给定指令操作将重放的指示。 处理器还包括解码单元，其可以解码指令并且响应于检测到指示，可以标记给定的指令操作。 调度器可以进一步禁止标记指令操作的发生，直到与被标记的指令相关联的状态良好。
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公开(公告)号：US07293162B2
公开(公告)日：2007-11-06
申请号：US10323337
申请日：2002-12-18
IPC分类号： G06F9/40
CPC分类号： G06F9/3836 , G06F9/3824
摘要： A scheduling scheme and mechanism for a processor system is disclosed. The scheduling scheme provides a reservation station system that includes a control reservation station and a data reservation station. The reservation station system receives an operational entry and for each operational entry it identifies scheduling state information, operand state information, and operand information. The reservation station system stores the scheduling state information and operand information as a control reservation station entry in the control reservation station and stores the operating state information and the operand information as a data reservation station entry in the data reservation station. When control reservation station entries are identified as ready, they are scheduled and issued for execution by a functional unit. The result from the functional unit is distributed within the control reservation station and the data reservation station for subsequent operational entries to use in preparation for scheduling and issuing those entries for execution.
摘要翻译： 公开了一种处理器系统的调度方案和机制。 调度方案提供包括控制预留站和数据预留站的预约站系统。 预约站系统接收操作条目，并且对于每个操作条目，其识别调度状态信息，操作数状态信息和操作数信息。 预约站系统将调度状态信息和操作数信息作为控制预约站条目存储在控制预约站中，并将操作状态信息和操作数信息作为数据预约站条目存储在数据保留站中。 当控制预约站条目被识别为就绪时，它们被调度和发布以供功能单元执行。 功能单元的结果分布在控制预留站和数据预留站中，用于随后的操作条目，以用于准备调度和发布那些用于执行的条目。
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公开(公告)号：US5830378A
公开(公告)日：1998-11-03
申请号：US600408
申请日：1996-02-12
申请人： Michael G. Butler
发明人： Michael G. Butler
CPC分类号： E04G13/00 , E02D2220/00
摘要： An assemblage which forms in-situ monolithic concrete slab-on-grade foundations is an internally collocating monolithic forming unit, which unit is typically light weight enough to be maneuvered intact. The unit is comprised of a number of form members and an overhead screed. The concrete-surface-defining form members, preferably sections of light-gage cold-formed metal, also serve as struts defining foundation horizontal geometry by having controlled lengths and interconnections. Corresponding pairs of squaring wires control geometry as well, and are removed before finishing the concrete slab. Temporary support of the forming unit is upon coarsely threaded stakes. Each stake screws into earth with a high speed pneumatic impact wrench, and quickly secures simple form support components such as a slab clip. Resulting connections provide subsequent adjustment of any form member independently, or the entire forming unit simultaneously, in any direction or rotation before securing it into place, and pouring a slab on grade foundation.
摘要翻译： 形成原位单块混凝土平板式地基的组合是内部配置的整体式成形单元，该单元通常重量足以完整地操纵。 该单位由许多形式成员和架空熨平板组成。 混凝土表面限定形式的构件，优选地是轻规格的冷成形金属部分，也用作通过具有受控长度和互连来定义基础水平几何形状的支柱。 相应的平面线对也控制几何形状，并且在完成混凝土板之前被移除。 成型单元的临时支撑是粗螺纹桩。 每个紧固件用高速气动冲击扳手拧入地面，并快速固定简单的支撑部件，如平板夹。 所得到的连接可以在将任何形式的构件固定在适当位置之前，随时调整任何形式的构件，或者整个成形单元同时在任何方向或旋转中，并将板坯浇筑在基础上。
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公开(公告)号：US08787058B2
公开(公告)日：2014-07-22
申请号：US13207749
申请日：2011-08-11
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is provided to the group of comparators, the match value corresponding to a binary value pair to be compared with the binary value stored in the pair of CAM elements. A positive match result value is output from a selected group of comparators via an output line in response to the comparison value matching the match value.
摘要翻译： 公开了一种用于比较内容可寻址存储器（CAM）元件的方法。 二进制值存储在一对CAM元素中。 将比较值提供给一组比较器，该比较值基于存储在该对CAM元件中的二进制值。 向比较器组提供匹配值，对应于要与存储在该对CAM元件中的二进制值进行比较的二进制值对的匹配值。 响应于匹配匹配值的比较值，通过输出线从所选择的一组比较器输出正匹配结果值。
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公开(公告)号：US20130039109A1
公开(公告)日：2013-02-14
申请号：US13207749
申请日：2011-08-11
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is provided to the group of comparators, the match value corresponding to a binary value pair to be compared with the binary value stored in the pair of CAM elements. A positive match result value is output from a selected group of comparators via an output line in response to the comparison value matching the match value.
摘要翻译： 公开了一种用于比较内容可寻址存储器（CAM）元件的方法。 二进制值存储在一对CAM元素中。 将比较值提供给一组比较器，该比较值基于存储在该对CAM元件中的二进制值。 向比较器组提供匹配值，对应于要与存储在该对CAM元件中的二进制值进行比较的二进制值对的匹配值。 响应于匹配匹配值的比较值，通过输出线从所选择的一组比较器输出正匹配结果值。
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公开(公告)号：US07743232B2
公开(公告)日：2010-06-22
申请号：US11779642
申请日：2007-07-18
申请人： Gene W. Shen , Bruce R. Holloway , Sean Lie , Michael G. Butler
发明人： Gene W. Shen , Bruce R. Holloway , Sean Lie , Michael G. Butler
IPC分类号： G06F9/24
摘要： A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode unit configured to store microcode entries. The processor may also include a remote microcode unit accessible by each of the processor cores. Any given one of the processor cores may be configured to generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by the given processor core, and to determine whether the particular microcode entry is stored within the respective local microcode unit of the given core. In response to determining that the particular microcode entry is not stored within the respective local microcode unit, the given core may convey a request for the particular microcode entry to the remote microcode unit.
摘要翻译： 具有分级微代码存储器的多核处理器。 处理器可以包括多个处理器核心，每个处理器核心被配置为独立地执行根据编程器 - 可见指令集架构（ISA）定义的指令。 每个核心可以包括被配置为存储微代码条目的相应的本地微代码单元。 处理器还可以包括可由每个处理器核心访问的远程微代码单元。 任何给定的一个处理器核心可以被配置为生成对应于特定微代码条目的给定微代码入口点，该特定微代码入口包括要由给定处理器核心执行的一个或多个操作，并且确定特定微代码条目是否存储在相应的本地 给定核心的微码单元。 响应于确定特定微代码条目不存储在相应的本地微代码单元内，给定的核心可以向远程微代码单元传达特定微代码条目的请求。
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