公开(公告)号：US20070117068A1

公开(公告)日：2007-05-24

申请号：US11284903

申请日：2005-11-23

申请人： Michael Nelms ,  Raymond Gordon ,  Lester Best

发明人： Michael Nelms ,  Raymond Gordon ,  Lester Best

IPC分类号： G09B9/02

CPC分类号： G09B9/02

摘要： Disclosed is a motion simulating device that includes a first scissor jack having a helical screw and a motor that rotates the helical screw of the scissor jack thereby raising or lowering the first scissor jack. Also included is a second scissor jack also having a helical screw and a motor that rotates the helical screw thereby raising or lowering the second scissor jack. At least one platform can be connected to the first and second scissor jacks. A controller is in communication with the first and second motors so that rotation of the helical screws of the first and second scissor jacks raises or lowers the scissor jacks thereby moving the platform up and down in accordance with movement of the scissor jacks. The controller can be a joystick, a steering wheel, foot pedals, a voice trigger, a gear shifter, roller ball, or any other device capable of translating mechanical energy into an electrical signal. The motion simulating device can also include at least one additional controller.

摘要翻译： 公开了一种运动模拟装置，其包括具有螺旋螺旋的第一剪刀千斤顶和使剪刀千斤顶的螺旋螺旋旋转的马达，从而升高或降低第一剪式千斤顶。 还包括也具有螺旋螺钉的第二剪刀千斤顶和旋转螺旋螺杆从而升高或降低第二剪刀千斤顶的马达。 至少一个平台可以连接到第一和第二剪刀千斤顶。 控制器与第一和第二电动机连通，使得第一和第二剪刀千斤顶的螺旋螺旋的旋转升高或降低剪刀千斤顶，从而根据剪刀插座的移动上下移动平台。 控制器可以是操纵杆，方向盘，脚踏板，语音触发器，换档器，滚球或能够将机械能转换成电信号的任何其他装置。 运动模拟装置还可以包括至少一个附加控制器。

公开(公告)号：US20050172194A1

公开(公告)日：2005-08-04

申请号：US10707971

申请日：2004-01-29

申请人： Jeffrey Dreibelbis ,  Kevin Gorman ,  Michael Nelms

发明人： Jeffrey Dreibelbis ,  Kevin Gorman ,  Michael Nelms

IPC分类号： G01R31/28 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/16 ,  G11C29/44

CPC分类号： G11C29/14 ,  G01R31/31724 ,  G01R31/3187 ,  G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72 ,  G11C2029/0401

摘要： Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

摘要翻译： 公开了一种用于嵌入式存储器阵列的混合内置自测（BIST）架构，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并使用BIST指令集与多个嵌入式存储器阵列进行通信。 一个高速测试逻辑块被并入被测试的每个嵌入式存储器阵列中，并以更高的频率在本地处理从独立BIST逻辑控制器接收的BIST指令。 高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器。 独立的BIST逻辑控制器使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构能够实现。

公开(公告)号：US20050120270A1

公开(公告)日：2005-06-02

申请号：US10707071

申请日：2003-11-19

申请人： Darren Anand ,  Kevin Gorman ,  Michael Nelms

发明人： Darren Anand ,  Kevin Gorman ,  Michael Nelms

IPC分类号： G06F11/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/56

CPC分类号： G11C29/56 ,  G11C29/14 ,  G11C29/56008 ,  G11C2029/5604

摘要： A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.

摘要翻译： 位故障映射电路通过利用从低速自动测试设备（ATE）测试器产生的高速倍增时钟，精确地生成诸如DRAM的嵌入式存储器的位故障映射。 该电路在ATE测试仪，被测嵌入式内存，内置自检（BIST）和内置冗余分析（BIRA）之间进行通信。 通过在遇到失败时暂停BIST测试电路，即BIST预期数据与从阵列读取的实际数据之间的不匹配，然后移位位故障数据，提供嵌入式DRAM存储器的精确位故障映射 使用低速ATE测试仪时钟关闭芯片。 此后，通过使用高速内部时钟再次运行BIST，从故障点恢复高速测试，以提供高速位Fail Map。