公开(公告)号：US11923195B2

公开(公告)日：2024-03-05

申请号：US17352851

申请日：2021-06-21

申请人： SAMSUNG ELECTRONICS CO., LTD. ,  iBeam Materials, Inc.

发明人： Junhee Choi ,  Vladmir Matias ,  Joohun Han

IPC分类号： H01L21/02

CPC分类号： H01L21/02502 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02496 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02598 ,  H01L21/02192 ,  H01L21/02266 ,  H01L21/02422 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02631

摘要： A single crystal semiconductor includes a strain compensation layer; an amorphous substrate disposed on the strain compensation layer; a lattice matching layer disposed on the amorphous substrate and including two or more single crystal layers; and a single crystal semiconductor layer disposed on the lattice matching layer, the lattice matching layer including a direction control film disposed on the amorphous substrate and including a single crystal structure, and a buffer layer including a material different from that of the direction control film, the buffer layer being disposed on the direction control film and including a single crystal structure.

公开(公告)号：US11881683B2

公开(公告)日：2024-01-23

申请号：US17090846

申请日：2020-11-05

申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

发明人： Constance J. Chang-Hasnain ,  Jiaxing Wang ,  Jonas H. Kapraun ,  Emil Kolev

IPC分类号： H01S5/183 ,  H01S5/30 ,  H01L21/02

CPC分类号： H01S5/18361 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02543 ,  H01L21/02546 ,  H01S5/3013 ,  H01S5/18311 ,  H01S2304/02 ,  H01S2304/04

摘要： A semiconductor device fabrication method in which a growing process is followed by a capping process in which a phosphor containing material cap layer is deposited over a final GaAs based layer. The wafer, containing many such substrates, can be removed from the reaction chamber to continue processing at a later time without creating an oxide layer on the final GaAs based layer. In continuing processing, a decomposition process selectively decomposes the phosphor containing material cap layer, after which a regrowing process is performed to grow additional layers of the device structure. The capping, decomposition and regrowth processes can be repeated multiple times on the semiconductor devices on the wafer during device fabrication.

公开(公告)号：US11788202B2

公开(公告)日：2023-10-17

申请号：US18046943

申请日：2022-10-17

申请人： Government of the United States, as represented by the Secretary of the Air Force

发明人： Vladimir Tassev

IPC分类号： C30B25/04 ,  H01L21/02 ,  C30B29/44 ,  C30B29/40 ,  C30B25/18 ,  G02F1/355 ,  C30B29/42 ,  C30B29/48 ,  C30B25/02 ,  H01L31/18

CPC分类号： C30B25/04 ,  C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  C30B29/406 ,  C30B29/42 ,  C30B29/44 ,  C30B29/48 ,  G02F1/3556 ,  H01L21/024 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02293 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02568 ,  H01L21/02658 ,  H01L31/1828 ,  G02F1/3558

摘要： A method of performing HVPE heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and ternary-forming gasses (V/VI group precursor), to form a heteroepitaxial growth of a binary, ternary, and/or quaternary compound on the substrate; wherein the carrier gas is Hz, wherein the first precursor gas is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the ternary-forming gasses comprise at least two or more of AsH3 (arsine), PH3 (phosphine), H2Se (hydrogen selenide), HzTe (hydrogen telluride), SbH3 (hydrogen antimonide, or antimony tri-hydride, or stibine), H2S (hydrogen sulfide), NH3 (ammonia), and HF (hydrogen fluoride); flowing the carrier gas over the Group II/III element; exposing the substrate to the ternary-forming gasses in a predetermined ratio of first ternary-forming gas to second ternary-forming gas (1tf:2tf ratio); and changing the 1tf:2tf ratio over time.

公开(公告)号：US20180358225A1

公开(公告)日：2018-12-13

申请号：US15562098

申请日：2016-05-27

申请人： Lars-Erik WERNERSSON

发明人： Lars-Erik Wernersson ,  Johannes Svensson ,  Anil Dey

IPC分类号： H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238

CPC分类号： H01L21/02381 ,  B82Y10/00 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/775

摘要： A method for fabrication of growing, in one growth run, at least one group of III-V n-type nanowires and at least one group of III-V p-type nanowires using gold particles, where the gold particles are of one size for the III-V n-type nanowires and one size for the III-V p-type nanowires.

公开(公告)号：US20180337082A1

公开(公告)日：2018-11-22

申请号：US15755860

申请日：2016-08-30

申请人： STC.UNM

发明人： Sanjay KRISHNA ,  Brianna KLEIN ,  Francesca CAVALLO ,  Seyedeh Marziyeh ZAMIRI

IPC分类号： H01L21/683 ,  H01L31/0352 ,  H01L31/0304 ,  H01L31/18 ,  H01L27/146

CPC分类号： H01L21/02631 ,  H01L21/02398 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02664 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68368

摘要： A method for forming a semiconductor structure, includes: providing a host substrate; forming at least one sacrificial layer having two or more group-V species over the host substrate; forming at least one semiconductor layer over the at least one sacrificial layer; and transferring at least a portion of the at least one semiconductor layer from the host substrate onto an alternate substrate.

公开(公告)号：US10070820B2

公开(公告)日：2018-09-11

申请号：US14265234

申请日：2014-04-29

申请人： Micro Nipple Technology Co., Ltd.

发明人： Juang-Tang Huang

IPC分类号： A61B5/00 ,  A61B5/15 ,  A61B5/05 ,  A61B5/145

CPC分类号： H01L31/035236 ,  A61B5/05 ,  A61B5/14514 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150969 ,  A61B5/150984 ,  A61B5/6833 ,  A61B5/6849 ,  A61B5/685 ,  A61B2562/046 ,  A61B2562/125 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L31/03046 ,  H01L31/105 ,  H01L31/1844 ,  Y02E10/544 ,  Y02P70/521

摘要： Transdermal microneedles continuous monitoring system is provided. The continuous system monitoring includes a substrate, a microneedle unit, a signal processing unit and a power supply unit. The microneedle unit at least comprises a first microneedle set used as a working electrode and a second microneedle set used as a reference electrode, the first and second microneedle sets arranging on the substrate. Each microneedle set comprises at least a microneedle. The first microneedle set comprises at least a sheet having a through hole on which a barbule forms at the edge. One of the sheets provides the through hole from which the barbules at the edge of the other sheets go through, and the barbules are disposed separately.

公开(公告)号：US09865706B2

公开(公告)日：2018-01-09

申请号：US15277394

申请日：2016-09-27

申请人： Applied Materials, Inc.

发明人： Xinyu Bao ,  Chun Yan

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66742 ,  H01L21/02057 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/8252 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/78681 ,  H01L29/78696

摘要： Embodiments described herein generally relate to methods and structures for forming precise fins comprising Group III-V elements on a silicon substrate. A buffer layer is deposited in a trench formed in the dielectric material on a substrate. An isolation layer is then deposited over the buffer layer. A portion of the isolation layer is removed allowing for a precisely sized Group III-V channel layer to be deposited on the isolation layer.

公开(公告)号：US20170345900A1

公开(公告)日：2017-11-30

申请号：US15527221

申请日：2014-12-23

申请人： Intel Corporation

发明人： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC分类号： H01L29/205 ,  H01L21/02 ,  H01L21/18

CPC分类号： H01L29/205 ,  H01L21/02455 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/182 ,  H01L21/185

摘要： Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170335444A1

公开(公告)日：2017-11-23

申请号：US15668026

申请日：2017-08-03

申请人： Applied Materials, Inc.

发明人： Zhiyuan YE ,  Errol Antonio C. SANCHEZ ,  Keun-Yong BAN ,  Xinyu BAO

IPC分类号： C23C8/02 ,  H01L21/02

CPC分类号： C23C8/02 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262

摘要： Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

公开(公告)号：US09761686B2

公开(公告)日：2017-09-12

申请号：US15187016

申请日：2016-06-20

申请人： SUMITOMO CHEMICAL COMPANY, LIMITED

发明人： Sadanori Yamanaka ,  Naohiro Nishikawa ,  Tsuyoshi Nakano

IPC分类号： H01L21/00 ,  H01L29/00 ,  H01L29/66 ,  H01L29/737 ,  H01L21/02 ,  H01L29/207

CPC分类号： H01L29/66318 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/207 ,  H01L29/7371

摘要： Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Such a semiconductor wafer may include a first semiconductor crystal layer, a second semiconductor crystal layer exhibiting a conductivity type that is different from the first layer, a third semiconductor crystal layer exhibiting the conductivity type of the first layer and having a larger band gap than the second semiconductor crystal layer, and a fourth semiconductor crystal layer exhibiting the conductivity type of the first layer and having a smaller band gap than the third semiconductor crystal layer. The fourth semiconductor crystal layer contains a first element that generates a first carrier of a corresponding conductivity type and a second element that generates a second carrier of a corresponding conductivity type.