公开(公告)号：US06788608B2

公开(公告)日：2004-09-07

申请号：US10209538

申请日：2002-07-30

申请人： Hieu Van Tran ,  William John Saiki ,  Jack Edward Frayer ,  Michael Stephen Briner

发明人： Hieu Van Tran ,  William John Saiki ,  Jack Edward Frayer ,  Michael Stephen Briner

IPC分类号： G11C700

CPC分类号： G11C5/145 ,  G11C11/56 ,  G11C16/30

摘要： A digital multilevel non-volatile memory integrated system includes an apparatus and method for high voltage, high precision pulsing generation. A voltage generator includes a low voltage high speed generator, a low voltage to high voltage high speed level translator, and a high voltage driver. A precise and stable high voltage level is attained across power supply, process, or temperature variation. The power may be optimized at the high voltage supply as tradeoff with power in the low voltage supply. A ping-pong operation sets up a high voltage level and the high voltage pulsing is output in a ping-pong fashion. A slew rate control circuit slows the input to achieve faster settling times. The high voltage is shaped by low voltage switching, HV fast switching and ramp circuit control. The high voltage pulsing may be fast and precise to permit real time control of the pulse parameters to adapt to memory cell attributes.

摘要翻译： 数字多电平非易失性存储器集成系统包括用于高电压，高精度脉冲发生的装置和方法。 电压发生器包括低压高速发生器，低压至高压高速电平转换器和高压驱动器。 通过电源，过程或温度变化实现精确稳定的高电压电平。 功率可以在高压电源下进行优化，因为在低电压电源中与功率进行权衡。 乒乓操作设置高电压电平，高压脉冲以乒乓方式输出。 转换速率控制电路减慢输入以实现更快的建立时间。 高压通过低压开关，高压快速开关和斜坡电路控制形成。 高压脉冲可以是快速和精确的，以允许脉冲参数的实时控制以适应存储器单元属性。

公开(公告)号：US07184345B2

公开(公告)日：2007-02-27

申请号：US11283195

申请日：2005-11-18

申请人： Hieu Van Tran ,  Jack Edward Frayer ,  William John Saiki ,  Michael Stephen Briner

发明人： Hieu Van Tran ,  Jack Edward Frayer ,  William John Saiki ,  Michael Stephen Briner

IPC分类号： G11C7/00

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C16/28

摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

摘要翻译： 数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。 读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。 高速负载提供高速感应。 宽输出范围在比较节点上提供高速的感测余量。 低阻抗输出驱动器驱动差分比较器的高噪声负载。 耦合到读出放大器的输入和输出的预充电电路增加了感测速度。 差分比较器具有包括模拟引导的架构。 参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。 参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

公开(公告)号：US06885600B2

公开(公告)日：2005-04-26

申请号：US10241266

申请日：2002-09-10

申请人： Hieu Van Tran ,  Jack Edward Frayer ,  William John Saiki ,  Michael Stephen Briner

发明人： Hieu Van Tran ,  Jack Edward Frayer ,  William John Saiki ,  Michael Stephen Briner

IPC分类号： G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C17/00

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/065 ,  G11C16/28

摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

摘要翻译： 数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。 读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。 高速负载提供高速感应。 宽输出范围在比较节点上提供高速的感测余量。 低阻抗输出驱动器驱动差分比较器的高噪声负载。 耦合到读出放大器的输入和输出的预充电电路增加了感测速度。 差分比较器具有包括模拟引导的架构。 参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。 参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

公开(公告)号：US07038960B2

公开(公告)日：2006-05-02

申请号：US10241442

申请日：2002-09-10

申请人： Hieu Van Tran ,  Jack Edward Frayer ,  William John Saiki ,  Michael Stephen Briner

发明人： Hieu Van Tran ,  Jack Edward Frayer ,  William John Saiki ,  Michael Stephen Briner

IPC分类号： G11C7/00

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C16/28

摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

摘要翻译： 数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。 读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。 高速负载提供高速感应。 宽输出范围在比较节点上提供高速的感测余量。 低阻抗输出驱动器驱动差分比较器的高噪声负载。 耦合到读出放大器的输入和输出的预充电电路增加了感测速度。 差分比较器具有包括模拟引导的架构。 参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。 参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。