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公开(公告)号：US08174287B2
公开(公告)日：2012-05-08
申请号：US12565133
申请日：2009-09-23
申请人： Michael German , Michel Ivgi , Roee Elizov , Shlomo Davidson , Yair Khayat
发明人： Michael German , Michel Ivgi , Roee Elizov , Shlomo Davidson , Yair Khayat
IPC分类号： H03K19/173
CPC分类号： H03K19/17752 , H03K19/17744
摘要： A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.
摘要翻译： 一种包括具有至少一个接口逻辑块连接的PLD的设备，用于在（i）布置成用于从外部处理器接收数据的总线和（ii）至少一个与所述PLD的JTAG接口连接的I / O寄存器之间传递数据， 其中所述接口逻辑块包括将总线上的数据转换为I / O寄存器的数据格式的逻辑。 一种处理器可编程PLD器件，包括（a）具有JTAG编程接口的可编程PLD，其支持PLD的实时重新编程，同时PLD的功能如编程; I / O寄存器连接I / O寄存器并与JTAG编程接口连接，其中I / O寄存器的PLD逻辑设计实现可以通过PLD的接口逻辑块从外部访问，并且其中， 接口逻辑块包括（i）外部处理器接口和（ii）PLD实现的I / O寄存器之间的PLD路径。
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公开(公告)号：US20080174283A1
公开(公告)日：2008-07-24
申请号：US11625942
申请日：2007-01-23
IPC分类号： G05F1/00
CPC分类号： H04L12/66
摘要： A communication card including a card substrate, a power interface adapted to receive power from a power source and distribute it to elements mounted on the card substrate and a ground start detection circuit on the card substrate. The card additionally includes an active current regulating circuit adapted to receive electrical power through the power interface, regulate a provided current responsive to the received electrical power and provide the regulated current to the ground start detection circuit.
摘要翻译： 一种通信卡，包括卡基板，电源接口，适于从电源接收电力并将其分配到安装在卡基板上的元件和卡基板上的接地起动检测电路。 卡还包括有源电流调节电路，其适于通过电源接口接收电力，响应于所接收的电功率来调节所提供的电流，并将调节的电流提供给地面起始检测电路。
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公开(公告)号：US20110068823A1
公开(公告)日：2011-03-24
申请号：US12565133
申请日：2009-09-23
申请人： MICHAEL GERMAN , MICHEL IVGI , ROEE ELIZOV , SHLOMO DAVIDSON , YAIR KHAYAT
发明人： MICHAEL GERMAN , MICHEL IVGI , ROEE ELIZOV , SHLOMO DAVIDSON , YAIR KHAYAT
IPC分类号： H03K19/173
CPC分类号： H03K19/17752 , H03K19/17744
摘要： A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.
摘要翻译： 一种包括具有至少一个接口逻辑块连接的PLD的设备，用于在（i）布置成用于从外部处理器接收数据的总线和（ii）至少一个与所述PLD的JTAG接口连接的I / O寄存器之间传递数据， 其中所述接口逻辑块包括将总线上的数据转换为I / O寄存器的数据格式的逻辑。 一种处理器可编程PLD器件，包括（a）具有JTAG编程接口的可编程PLD，其支持PLD的实时重新编程，同时PLD的功能如编程; I / O寄存器连接I / O寄存器并与JTAG编程接口连接，其中I / O寄存器的PLD逻辑设计实现可以通过PLD的接口逻辑块从外部访问，并且其中， 接口逻辑块包括（i）外部处理器接口和（ii）PLD实现的I / O寄存器之间的PLD路径。
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