公开(公告)号：US08174287B2

公开(公告)日：2012-05-08

申请号：US12565133

申请日：2009-09-23

申请人： Michael German ,  Michel Ivgi ,  Roee Elizov ,  Shlomo Davidson ,  Yair Khayat

发明人： Michael German ,  Michel Ivgi ,  Roee Elizov ,  Shlomo Davidson ,  Yair Khayat

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  H03K19/17744

摘要： A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.

摘要翻译： 一种包括具有至少一个接口逻辑块连接的PLD的设备，用于在（i）布置成用于从外部处理器接收数据的总线和（ii）至少一个与所述PLD的JTAG接口连接的I / O寄存器之间传递数据， 其中所述接口逻辑块包括将总线上的数据转换为I / O寄存器的数据格式的逻辑。 一种处理器可编程PLD器件，包括（a）具有JTAG编程接口的可编程PLD，其支持PLD的实时重新编程，同时PLD的功能如编程; I / O寄存器连接I / O寄存器并与JTAG编程接口连接，其中I / O寄存器的PLD逻辑设计实现可以通过PLD的接口逻辑块从外部访问，并且其中， 接口逻辑块包括（i）外部处理器接口和（ii）PLD实现的I / O寄存器之间的PLD路径。

公开(公告)号：US20110068823A1

公开(公告)日：2011-03-24

申请号：US12565133

申请日：2009-09-23

申请人： MICHAEL GERMAN ,  MICHEL IVGI ,  ROEE ELIZOV ,  SHLOMO DAVIDSON ,  YAIR KHAYAT

发明人： MICHAEL GERMAN ,  MICHEL IVGI ,  ROEE ELIZOV ,  SHLOMO DAVIDSON ,  YAIR KHAYAT

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  H03K19/17744

摘要： A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.

摘要翻译： 一种包括具有至少一个接口逻辑块连接的PLD的设备，用于在（i）布置成用于从外部处理器接收数据的总线和（ii）至少一个与所述PLD的JTAG接口连接的I / O寄存器之间传递数据， 其中所述接口逻辑块包括将总线上的数据转换为I / O寄存器的数据格式的逻辑。 一种处理器可编程PLD器件，包括（a）具有JTAG编程接口的可编程PLD，其支持PLD的实时重新编程，同时PLD的功能如编程; I / O寄存器连接I / O寄存器并与JTAG编程接口连接，其中I / O寄存器的PLD逻辑设计实现可以通过PLD的接口逻辑块从外部访问，并且其中， 接口逻辑块包括（i）外部处理器接口和（ii）PLD实现的I / O寄存器之间的PLD路径。