摘要:
A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to receive a clock signal and is coupled to a low threshold inverter in the first branch and a high threshold inverter in the second branch. The latch is adapted to receive the clock signal and is coupled to the first branch, while the logic is coupled to the node between the first branch and the latch, an output of the latch, and the second branch so that it can output a clock detection signal.
摘要:
An apparatus receives an indicating signal representing a parameter at a monitoring locus and includes: (a) A first measuring unit having a first input coupled for selectively receiving the indicating signal and presenting a first output signal that includes a first monitoring signal representing change in the indicating signal during a first time interval and a first benchmark signal indicating change imparted to signals by the first measuring unit. (b) A second measuring unit having a second input coupled for selectively receiving the indicating signal and presenting a second output signal that includes a second monitoring signal representing change in the indicating signal during a second time interval and a second benchmark signal indicating change imparted to signals by the second measuring unit. (c) An accumulating and indicator unit coupled for receiving and evaluating the first and second output signals and generating an indicator signal that represents the evaluating.
摘要:
A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to receive a clock signal and is coupled to a low threshold inverter in the first branch and a high threshold inverter in the second branch. The latch is adapted to receive the clock signal and is coupled to the first branch, while the logic is coupled to the node between the first branch and the latch, an output of the latch, and the second branch so that it can output a clock detection signal.
摘要:
A battery charge/discharge monitor circuit (10) is operable to be disposed in a battery pack (12) which can be connected to a battery (13). The monitor circuit (10) is operable to be connected to an external CPU (24) or similar system through a single wire communication port (22) for transferring information back and forth. There is also provided an external signal on a line (30) for indicating charge or discharge activity in the monitor circuit (10). The monitor circuit (10) is operable to collect information regarding the amount of charge input to the battery and the length of time that the charge is input to the battery and also the amount of charge that is removed from the battery and the length of time that the charge is removed. This information is stored in a memory block (62) for later access by the external CPU (24). This system also provides offset information to provide some type of compensation for non-linearities of the part. This offset is determined during a calibration operation which operates over a long period of time during a period of inactivity. Regulation circuitry is operable to provide internal regulation to the circuitry with an external JFET (20).